In 150 mm and 200 mm silicon carbide power-device wafer production, diamond-wire slicing and coarse diamond grinding leave a subsurface damage zone that must be removed before epitaxy. Zirconia polishing slurry of Electronic/EL grade is diluted at the point of use with ultrapure water in a 1:4–1:9 volumetric ratio and adjusted to pH 2.8–4.5 with semiconductor-grade organic acid. The dispersion has a median particle size of 180–250 nm measured by dynamic light scattering per ISO 22412:2017 and zeta potential above +15 mV per ISO 13099-1:2012. Processing is performed on a single-side rotary polisher with a hard polyurethane pad, platen speed 50–80 rpm, carrier downforce 4–7 psi, and slurry flow 120–250 mL/min. The Si-face removal rate remains below 1 µm/h, which is a known constraint of the chemically inert basal plane; C-face rates may be higher but produce rougher surfaces. Final surface roughness is controlled to 0.2–0.4 nm Ra by AFM, and total trace metal content is held below 1 ppm by ICP-MS after closed-vessel acid digestion. This finish supports epi-ready 600 V and 1.2 kV SiC MOSFET and Schottky barrier diode production. Wafer fabs typically enforce acceptance limits derived from SEMI C43 impurity control methods and RoHS 2011/65/EU.

What Limits Edge Chipping in Sapphire CMP for GaN-on-Sapphire RF Devices?

Edge chipping in sapphire wafer polishing is controlled less by bulk removal rate than by the pad pressure ramp and the particle size distribution of the zirconia slurry. For 100-mm and 150-mm sapphire wafers destined for gallium nitride epitaxy, the Electronic/EL grade slurry is supplied at 5–15 wt% solids and diluted 1:3–1:8 with point-of-use ultrapure water; pH is held at 2.0–4.0 using a non-metallic organic acid system. Median particle size is 50–120 nm by ISO 22412:2017, and large-particle counts above 0.5 µm are specified below 100/mL to reduce microscratch density. Double-side polishing is run on a polyurethane pad with initial downforce of 2 psi, increased stepwise to 5 psi after wafer edge round-off is confirmed. Platen speed is 40–80 rpm, and slurry flow is 100–200 mL/min per side. Final surface roughness is 0.1–0.3 nm Ra on a 10 x 10 µm AFM scan. Total alkali and transition metal burden is held below 0.5 ppm because sodium and iron degrade GaN nucleation. The polished sapphire wafers become epi-ready carriers for radio-frequency GaN HEMT and micro-LED production. Compliance audits reference ISO 22412:2017, ISO 13099-1:2012, and RoHS 2011/65/EU.

Lithium tantalate and lithium niobate wafer thinning for 5G n77/n79 SAW filters requires a polishing step that removes backgrinding damage without introducing subsurface cracks that broaden acoustic losses. The zirconia slurry is diluted 1:5–1:12 at point-of-use and has a median particle size of 80–150 nm measured by ISO 22412:2017; solids loading is 1–8 wt%, and pH is maintained between 3.5 and 6.0. CMP is performed on a wax-mounted double-side polisher with low downforce 2–5 psi, platen speed 30–50 rpm, and slurry flow 0.4–0.8 L/min to limit wafer bow. For wafers of 100–150 mm diameter thinned to 100–250 µm, thickness variation is held below 1 µm, with final surface roughness 0.2–0.5 nm Ra. Iron and copper contamination are specified below 0.5 ppm because transition metals migrate under acoustic power and shift resonator Q. Finished lithium tantalate and lithium niobate substrates are processed into SAW/BAW duplexers and filter arrays used in 5G radio-frequency front-end modules.

When PZT Wafers Drop Below 50 µm for Piezoelectric MEMS

The polishing of PZT-5A and PZT-5H wafers below 50 µm imposes a mechanical ceiling on downforce because ferroelastic domain motion and brittle intergranular fracture are aggravated above 4 psi. The zirconia slurry for piezoelectric MEMS is diluted 1:6–1:10; solids are 5–15 wt%, median particle size 100–200 nm by ISO 22412:2017, and pH is buffered at 4.0–7.0. Single-side polishing on a soft-to-hard pad stack with platen speed 40–70 rpm and slurry flow 100–250 mL/min produces a final thickness of 20–50 µm, wafer bow below 10 µm, and surface roughness 0.3–0.6 nm Ra. The process removes saw- and grinding-induced microcracks while limiting lead-rich debris release and avoiding iron contamination above 0.5 ppm. Because PZT contains lead, terminal component compliance is assessed under RoHS 2011/65/EU Annex III lead in piezoelectric ceramics; waste slurry is handled under EC 1907/2006. Polished PZT wafers are used in piezoelectric micro-machined ultrasonic transducer fingerprint sensors, particle sensors, and medical transmitters.

Panel-level temporary bonding on glass carriers requires a zirconia CMP step to prevent void formation and redistribution-layer thickness drift on 510 x 515 mm substrates. The slurry is diluted 1:2–1:5; solids are 2–10 wt%, median particle size 50–100 nm, and pH is 2.0–4.0. Large-panel double-side polishers run at platen speed 20–40 rpm, downforce 1–3 psi, and slurry flow 0.8–1.5 L/min. Total thickness variation across the panel is held below 2 µm, edge roll-off below 0.2 µm over the outer 10 mm, and roughness below 0.5 nm Ra. Alkali extraction is controlled below 1 ppm because sodium and potassium migration into adhesive layers alters temporary bond release force. Such carriers support redistribution-layer build-up and chip-first fan-out wafer-level packaging.

NiP Hard-Disk Substrate Polishing to Sub-0.3 nm Ra with Zirconia Abrasive

For 95-mm and 65-mm nickel-phosphorus plated aluminum hard-disk blanks, zirconia slurry is used after precision lathe turning and diamond finishing to remove waviness and surface defects that would degrade perpendicular magnetic recording. The slurry has median particle size 50–100 nm, solids 2–8 wt%, dilution 1:2–1:6, and pH 2.5–4.0. Double-side polishing is conducted on polyurethane pads with platen speed 30–60 rpm, downforce 1–3 psi, and slurry flow 0.5–1.2 L/min. A final touch-polish step reduces roughness to 0.2–0.3 nm Ra measured by AFM over 5 x 5 µm, with laser scanning limited to fewer than 10 defects per surface for scratches larger than 0.2 µm. Trace metal transfer from pad and slurry is controlled below 0.5 ppm total transition metals because cobalt and iron in plated media sites alter magnetic coercivity. The polished substrates are plated with cobalt-based recording layers and form hard-disk media used in enterprise and nearline storage. Compliance references ISO 22412:2017 for particle size, ASTM E70-19 for pH, and customer-specific defect maps aligned to ISO 14644-1.

HTCC Via Capture Requires Sub-1 µm Height Variation Before Copper Plating

High-alumina 96% Al₂O₃ and high-temperature co-fired ceramic substrates require planarization after via fill and before thin-film copper metallization. A zirconia slurry with median particle size 150–350 nm, solids 10–25 wt%, and point-of-use dilution 1:3–1:8 is applied after precision lapping. pH is controlled between 3.0 and 6.0; the acidic range avoids excessive grain-boundary attack while maintaining mechanical removal. Platen speed is 30–60 rpm, downforce 3–6 psi, and slurry flow 100–300 mL/min on a low-nap polyurethane pad. The process reduces surface roughness from lapped 0.2–0.5 µm Ra to 0.5–1.0 nm Ra and improves via capture accuracy by reducing local taper height variation to below 1 µm. The polished substrates are used for high-power module baseplates and hermetic RF package bodies. Compliance is based on ISO 14644-1 cleanroom particulate control, ASTM E70-19 pH verification, and customer-specific ionic contamination limits derived from RoHS 2011/65/EU.