In 300 mm logic and memory fabrication, wet tungsten recess after chemical vapor deposition addresses plug height reduction before barrier or low-k dielectric coverage. The electronic/EL-grade etchant is typically a stabilized aqueous hydrogen peroxide formulation supplied at 20–30 wt% H₂O₂ with an inorganic stabilizer package and a pH held between 6.5 and 8.5 for TiN liner compatibility. Process equipment includes PFA-lined single-wafer spray processors with point-of-use 0.02 µm filtration, or recirculated immersion wet benches fitted with Teflon heat exchangers and 0.8–1.2 MHz megasonic transducers. Tungsten removal proceeds through oxidation to soluble tungstate: alkaline systems follow W + 3H₂O₂ + 2OH^- → WO₄^2- + 4H₂O, while near-neutral acidic systems generate hydrated tungstic acid. In recess applications, useful etch rate at 45 °C is generally 60–120 nm/min; at 35 °C the rate falls below 40 nm/min on patterned wafers, and above 60 °C peroxide decomposition shortens the working window. The process is monitored by ellipsometry or sheet-resistance end-point on blanket monitors, with within-wafer non-uniformity held below 5% on 300 mm substrates. TiN selectivity remains above 100:1 because the oxidized TiN surface passivates under mildly alkaline conditions, but excursions above pH 9.5 produce measurable TEOS oxide loss greater than 2 nm/min and are avoided. Drag-in of transition-metal cations from upstream plating or CMP tools accelerates H₂O₂ decomposition; the bath is discarded or replenished when Fe exceeds 50 ppb or oxidant drops below 90% of initial concentration. Wafer processing under ISO 14644-1:2015 Class 3 or better minienvironment is standard, and chemical handling equipment is validated to SEMI S2-0718.

Table 1. Target process window for tungsten recess qualification.

On production lines, the same chemistry is used for contact plug recess after tungsten CMP by limiting removal to 15–40 nm. Within-die loading effects are controlled by wafer rotation speed, fresh etchant delivery, and backside cooling, with dense via arrays showing lower local etch rate than isolated features due to oxidant depletion. Post-etch rinsing with ultrapure water per ASTM D5127-18 is performed for 60–120 s in rapid dump rinsers, followed by N₂ spin-dry. The limitation of immersion-bath operation is finite bath life: production lots exceeding 50 wafers/gal commonly show rate drift greater than 15% unless real-time concentration feed-and-bleed is used. Etchant suppliers provide lot-specific certificates with ICP-MS detection limits at or below 5 pptw for critical cations; incoming inspection uses ISO 17294-2:2016 for trace-metal verification. For particles at ≥0.1 µm, acceptance is typically ≤30 particles/mL by laser particle counting, because particles are a direct source of post-etch defects on low-k dielectrics.

MEMS Sacrificial Tungsten Release in Potassium-Free Hydrogen Peroxide Etchants

For MEMS surface micromachining, a sputtered or evaporated tungsten layer serves as a sacrificial platform when the structural material is silicon oxide, silicon nitride, or polymer. The potassium-free hydrogen peroxide etchant removes tungsten without introducing mobile potassium ions that degrade CMOS compatibility. In anodic bonding or thin-film encapsulation flows, the tungsten is deposited at 20–300 nm thickness; etch release is typically executed in a static PFA beaker or a wafer cassette immersion bath at 25–40 °C. The etch is isotropic, and lateral undercut under a 2 µm wide anchor commonly reaches 1–2 µm from each edge by the time vertical thickness clears. Release time is calculated from bulk etch rate and thickness; for 100 nm tungsten at 30 °C in a 20 wt% H₂O₂ formulation, published data for this specific configuration is limited, but process sheets generally budget 4–10 min including over-etch. The exposed underlying silicon dioxide remains intact if bath pH is below 4.5; higher-pH formulations roughen thermal oxide at 0.5–2 nm/min. MEMS structures are then transferred to an IPA vapor dryer because water rinsing after tungsten release can collapse freestanding beams with stiffness below 1 N/m. The principal production bottleneck is not etch rate but accumulation of dissolved tungsten in the bath above 500 ppm, at which point etch rate drops by more than 20% due to peroxide exhaustion and complexation. Recirculation through a 0.05 µm filter is not sufficient to remove soluble tungstate; partial bath replacement or continuous feed-and-bleed is required for lot sizes above 25 wafers.

Flat-panel display fabrication lines for active-matrix liquid-crystal or organic light-emitting-diode backplanes use sputtered tungsten gate metallization in some devices because of its low resistivity and high-temperature compatibility with subsequent SiN_x deposition. The tungsten etchant is applied as a wet strip after photoresist patterning, with critical-dimension loss controlled by temperature, concentration, and over-etch time. In a Gen 6 inline coater/developer wet station, the etchant is dispensed through a 0.1 µm polypropylene filter at 23–35 °C, followed by a deionized water cascade rinse and air-knife dry. The target etch depth for a 200 nm sputtered tungsten gate is 180–220 nm; the process is qualified by optical emission spectroscopy end-point on test coupons and by SEM cross-sections at panel corners and center. Etch uniformity across a 1500 × 1850 mm glass sheet must remain within ±10% of the mean to avoid gate-line resistance skew. A key compatibility issue is the etch of exposed aluminum or copper source-drain layers; therefore the chemistry is selected to hold aluminum removal below 5 nm at the tungsten end-point. Production experience indicates that silane-derived SiN_x sidewall deposits can retard local etch at step edges, producing tungsten stringers if over-etch is less than 30% of total etch time. Immersion-type batch spray processing is preferred over static etching because fresh etchant impingement removes dissolved tungstate from the exposed surface and reduces microloading under narrow gate lines.

How Does Meniscus Control Affect Tungsten Microelectrode Tip Taper?

For tungsten microelectrode arrays used in neurophysiology, the etchant shapes a cylindrical or wire-form tungsten substrate into a tapered tip with a radius of curvature below 1 µm. The process is pin-hole meniscus etching in a hydrogen peroxide–based bath, where the wire is positioned vertically and the etchant wets a defined length. Tip taper angle is governed by vertical meniscus height, bath surface tension, and etch time; a shorter meniscus of 3–5 mm yields a blunt taper of 20–30°, while a taller meniscus of 8–15 mm yields a sharper profile below 10° full angle. The etchant is typically diluted to 5–15 wt% H₂O₂ with controlled pH 2–4 to slow isotropic tip attack and permit optical inspection. Etch rates at 25 °C for 25–50 µm diameter tungsten wire are typically 50–150 nm/min; the process is stopped when tip diameter falls below 5 µm or when electrical impedance at 1 kHz reaches 0.5–2.0 MΩ in phosphate-buffered saline. The production failure mode is asymmetric taper caused by convective flow or bubble pinning at the meniscus; this is mitigated by low-vibration mounting, nitrogen-saturated etchant to reduce dissolved gas, and a slow withdrawal rate of 0.1–0.5 mm/min. Potassium-containing additives are excluded because residual potassium at the tip shifts the recorded extracellular potential baseline. After etching, wire bundles are rinsed in ASTM D5127-18 ultrapure water for 5 min and dried in a vacuum oven at 60–80 °C to prevent water meniscus-induced tip bending. This application does not require the same cation cleanliness as CMOS, but the etchant must be free of particulate agglomerates above 0.2 µm to avoid tip coating defects during subsequent Parylene-C insulation.

When a Patterned Tungsten Resistor Is Required on Silicon

When a thin-film tungsten resistor is required on silicon, the etchant defines resistor length and width after lift-off or photoresist patterning. Sputtered tungsten films of 50–300 nm thickness are wet-etched in a quiescent PFA bath at 25–45 °C with 10–20 wt% H₂O₂; resistor linewidth is verified by four-point probe sheet resistance and optical CD measurement, because wet undercut removes approximately 0.5–1.0 times the film thickness from each edge. If a 100 nm film is etched for an over-etch of 30%, final linewidth loss is 60–120 nm per edge, which must be included in the mask bias. The etch process exhibits a surface oxide lag at the start: native WOx and photoresist residues delay the first 10–15 nm removal by 60–120 s. The delay is compensated in production by a short oxygen plasma descum before the wet etch. After wet patterning, the wafer is immersed in deionized water for 5 min to quench peroxide carry-out, then spin-dried in a single-wafer module with 1500–2000 rpm rotation for 30 s. Lateral etch uniformity is better than ±5% when the bath is continuously stirred at 100–300 rpm and the tungsten concentration is kept below 500 ppm. A known limitation is that tungsten etchant attacks exposed aluminum bond pads; when the resistor is integrated with Al interconnects, the aluminum surface must be masked or the wet etch time constrained to avoid pad roughening beyond 5 nm/min. The process is not suitable for sub-0.5 µm resistor gaps because isotropic undercut closes the gap with yields below 60% on contact strings.