What Governs Etch Stop Behavior in High-Aspect-Ratio Silicon Nitride Slit Etch for 3D NAND?

Electronic/EL grade trifluoromethane containing 99.999 mol% CHF₃ after point-of-use purification is admitted to the gas manifold of a dual-frequency capacitively coupled plasma etch chamber. The chamber processes 300 mm patterned wafers with alternating silicon oxide and silicon nitride layers at stack thickness above 4 µm. In this configuration CHF₃ is not used as a bulk etchant. It functions as the polymer-forming precursor that balances fluorine radical concentration against fluorocarbon film deposition on sidewalls. A representative feed gas ratio of CHF₃/CF₄/O₂/Ar at 20:40:8:120 sccm sustains a plasma at 12 Pa to 28 Pa. Source power is applied at 60 MHz. Bias power is swept from 1.5 kW to 4.5 kW. This range is reported in plasma etching literature for trench aspect ratios above 30:1. The O₂ fraction is limited because excessive oxygen scavenging removes carbon polymer and exposes shoulder surfaces to uncontrolled lateral etch. Endpoint is controlled by optical emission spectroscopy on the CN emission at 387 nm or N₂ emission at 337 nm. Termination is triggered after a 10% overetch interval to clear remaining silicon nitride at the trench bottom. Products from this operation are high-density 3D NAND string arrays with staircase contacts and slit isolation trenches in devices of 200-layer-class or higher. The main operational boundary is the drift in polymer thickness on chamber walls. After more than 50 RF hours without dry chamber cleaning, CF₂/CHF₃ recombination on wall surfaces shifts. This causes a reduction in bottom polymer removal and an increase in micro-masking defects. Gas purity associated with SEMI C3 and point-of-use metal-filter practice maintain transition metal contamination below 1 ppbw in the gas stream. That limit protects threshold voltage stability in charge-trapping nitride films.

Etch stop defects occur when the CHF₃-derived fluorocarbon layer at the trench bottom exceeds the ion energy required for removal. In 3D NAND stacks, the silicate/nitride multilayer creates different sputter yields. The bias power ramp is therefore synchronized with the layer count. The process typically uses pressure ramping from 25 mTorr to 45 mTorr during the landing step. The final step raises CHF₃ flow to 30 sccm and suppresses CF₄ to 10 sccm to increase oxide-to-nitride selectivity during the overetch. Wafer-less chamber cleaning is performed with O₂ or NF₃ plasma between lots. Published data for this specific managed-CHF₃ ramp configuration is limited. Production-scale data from etch equipment manufacturers indicate that uncontrolled wall temperature drift above ±5 °C on ceramic dome surfaces changes fluorocarbon film thickness enough to shift critical dimension by ±2 nm.

Silicon Dioxide Via Patterning in Dual Damascene Back-End-of-Line

Logic back-end dielectric etching uses CHF₃ in binary or ternary mixtures with CF₄ and Ar to open vias through silicon oxide films over copper dual damascene structures. The role of CHF₃ is to generate CF₂ and CHF₂ radicals that passivate via sidewalls. The CF₄ component supplies atomic fluorine for bulk oxide removal. A common process window on 13.56 MHz RIE platforms mixes CHF₃ and CF₄ at ratios from 1:3 to 1:1. Ar dilution ranges from 50% to 70%. Chamber pressure is maintained at 40 mTorr to 80 mTorr. This mixture produces fluorocarbon sidewall films thick enough to maintain via sidewall angles at 88°–89° while still allowing oxide etch rates above 300 nm/min on 300 mm wafers. The process stops on a silicon nitride or silicon carbide etch-stop layer. The elevated CHF₃ fraction increases oxide-to-nitride selectivity by reducing nitride sputtering through thicker polymer deposition. Compliance follows SEMI C3 gas specifications and cleanroom particle limits under ISO 14644-1:2015 Class 3. The terminal device is a 28 nm-class or 14 nm-class CMOS logic chip with copper/low-κ interconnects. Via diameters range from 45 nm to 90 nm depending on metal level.

A significant processing constraint in low-κ integration is the accumulation of fluorocarbon polymer inside the via after the main etch. In dual damascene flows, a subsequent in situ Ar/O₂ sputter step removes the polymer. However, oxygen partial pressure above 10% damages porous SiCOH sidewalls. Modern etchers therefore split the CHF₃/CF₄ recipe into a bulk-etch step and a short post-etch polymer breakthrough step. Production data show that chamber seasoning with a CHF₃-rich plasma immediately before lot start reduces first-wafer via CD variation. The wall fluorocarbon coverage reaches a quasi-steady state. Without this pre-coat, the first one to three wafers can exhibit via critical dimension deviations outside the ±5% post-etch inspection limit. Oxygen and moisture in the CHF₃ supply must be below 1 ppmv each. Water dissociation in the plasma increases oxygen radical flux. That flux erodes the sidewall passivation polymer during high-aspect-ratio via processing.

In array fabrication for thin-film transistor liquid crystal displays and oxide semiconductor OLED backplanes, silicon nitride passivation layers are patterned over gate and source/drain electrodes on substrates up to 2.2 m × 2.5 m. Large-area plasma etching systems use linear inductively coupled plasma or capacitively coupled plasma sources. CHF₃ is added to CF₄ and O₂ to tune the C/F ratio in the discharge. On an 8.5-generation substrate, a representative feed gas ratio of CHF₃/CF₄/O₂ at 15:80:12 sccm per linear source exposes the silicon nitride at working pressures between 20 mTorr and 60 mTorr. The objective is to clear the passivation layer without overetching the thin amorphous silicon or indium gallium zinc oxide channel beneath. Etch uniformity across the substrate is monitored by multi-point spectroscopic ellipsometry after etching. In production, non-uniformity above 3% of the pre-etch silicon nitride thickness triggers source gas flow rebalancing. The terminal products are TFT backplanes for LCD television panels and OLED displays. Passivation via openings have widths from 2 µm to 8 µm.

The use of CHF₃ in flat panel processing is constrained by the need to minimize plasma-induced electrical damage to the channel layer. Excess CHF₃ increases the fluorocarbon film thickness on the photoresist edge and can create a tapered via profile. Insufficient CHF₃ permits lateral undercut of the silicon nitride beneath the resist. Large-area etchers therefore maintain substrate temperature below 80 °C during the process. Pulsed RF is used at duty cycles from 20% to 50% to reduce charge accumulation. Gas quality requirements follow SEMI C3 electronic-grade limits. Distributed gas lines on a Gen 8.5 line are longer than on a wafer fab tool. Point-of-use purifiers are installed at each process chamber to remove moisture and metallic impurities. Moisture ingress above 1 ppmv at the chamber inlet alters the CHF₃-to-CF₄ dissociation balance. The resulting drift produces contact resistance variation across the display panel.

If SF₆ Is Excluded From MEMS Release, What Does CHF₃ Offer for Sacrificial Silicon Nitride Etching?

Micromachined inertial sensors and RF MEMS devices require removal of sacrificial silicon nitride without attacking underlying monocrystalline silicon or aluminium metallization. When sulfur hexafluoride is excluded from the release sequence because of its high fluorination strength and etch-rate risk to silicon, a CHF₃/O₂/Ar plasma can provide a slower and more controllable nitride-only removal step. A remote inductively coupled plasma source with a downstream stage reduces ion bombardment. This allows near-isotropic removal of sacrificial nitride in cavities with lateral dimensions under 5 µm. The process operates at pressures above 100 mTorr, often 150–300 mTorr. CHF₃/O₂ ratios range from 2:1 to 5:1. Oxygen suppresses excessive fluorocarbon deposition but must be kept below the threshold where silicon etching accelerates. The end products are accelerometers, gyroscopes, pressure sensors, and resonators with released micromechanical structures. Selectivity of the plasma to silicon is maintained above 10:1 in production by monitoring the SiF emission at 440 nm during the release step.

Stiction is not solved by CHF₃. It is managed by downstream processing after the release etch, such as supercritical CO₂ drying or vapor-phase deposition of a hydrophobic monolayer. The operational boundary for CHF₃ release is its inability to remove thick sacrificial layers rapidly. Published data for this specific configuration is limited. The method is used where etch-rate precision is more valuable than process throughput. The gas purity requirement in MEMS release is stricter than in decorative etching. SEMI C3 electronic-grade limits for metals and water protect the exposed aluminium pads from corrosion. Fluorine residues left on released structures must be removed by an oxygen plasma strip and a deionized water rinse. Without this removal, long-term drift in device resonant frequency can occur.

Before production wafers enter a dielectric etch chamber, conditioning of ceramic chamber walls is performed using electronic-grade CHF₃. In this indirect application, CHF₃ flows into an empty chamber with Ar as carrier gas. A plasma is struck at 20 mTorr to 50 mTorr. Source power is set between 500 W and 1,500 W. The conditioning step lasts 60 s to 300 s. The plasma deposits a fluorocarbon polymer film on the chamber dome, electrostatic chuck edges, and exposed ceramic surfaces. This film neutralizes the variable recombination rate of fluorine radicals on chamber walls after wet cleaning or parts replacement. First-wafer etch rate and profile stabilize. The gas used for conditioning must be the same electronic-grade CHF₃ used in production. Trace water and CO₂ in lower-purity gas shift the polymer composition from CF₂-rich to oxygenated carbon. That shift changes wall recombination coefficients. On a production line, failure to perform this preconditioning after a chamber clean can cause first-wafer silicon dioxide etch rate drift exceeding 5% from lot mean. In-line optical thickness metrology detects this drift.

The chamber conditioning step still requires exhaust gas abatement because CHF₃ dissociation products and unreacted gas pass through the dry pump. Semiconductor fab permits typically limit total fluorinated gas emission based on destruction or recovery efficiency. Thermal abatement units operating above 1,000 °C or catalytic units are used. The process is not separable from production. Chamber-conditioning gas sequencing is stored in the etch tool recipe as a pre-production event. Its duration is adjusted based on mass spectrometry measurement of chamber exhaust. No standardized test exists for this application. Equipment manufacturers recommend conditioning time based on chamber water partial pressure after a wet clean. Conditioning continues until residual water partial pressure falls below 1×10⁻⁷ Torr.

Silicon Oxynitride Hardmask Removal Without Gate Oxide Consumption

Advanced logic gate patterning uses silicon oxynitride hardmasks on top of high-κ dielectric films. After plasma etching of the underlying silicon or metal gate, the oxynitride hardmask is removed in a post-etch step that must not consume the gate oxide. A CHF₃/CF₄/O₂ mixture in an inductively coupled plasma chamber at 5 mTorr to 15 mTorr removes the oxynitride at rates below 20 nm/min. The low rate permits precise endpoint control. The CHF₃ fraction is kept above 50% of the fluorocarbon feed to generate a protective fluorocarbon film on the high-κ material. Oxygen is limited to 1–2 sccm. Endpoint detection by optical emission spectroscopy monitors CN emission at 386 nm. That emission falls sharply when the oxynitride is cleared. The terminal product is a FinFET or gate-all-around transistor gate stack where oxide loss after hardmask removal is below 0.3 nm.

The limiting factor in this step is the buildup of fluorocarbon polymer on the wafer edge. If CHF₃ is used at high partial pressure without adequate Ar dilution, polymer can lift off in later wet cleaning stages and create particle defects. A short Ar/O₂ plasma clean therefore follows the CHF₃ removal step. Its duration is restricted to 15 s to avoid oxidation of metal gate surfaces. Electronic-grade CHF₃ purity is critical because metal impurities can become trapped in the gate stack and shift work function. The gas must meet SEMI C3 limits for transition metal content. Point-of-use filtration on the gas line uses 5 nm particle filters. Moisture in the gas line must be below 1 ppmv. Water in the plasma generates hydroxyl radicals that attack the high-κ dielectric.