On 200 mm and 300 mm tungsten contact lines, the Ti/TiN bilayer beneath CVD-W is exposed after bulk tungsten polishing and must be cleared without eroding the underlying TEOS or FSG dielectric. The as-supplied slurry is typically formulated with 3–8 wt% colloidal or fumed silica/alumina abrasive, adjusted to pH 2.5–3.8 (ASTM E70), containing 0.5–1.5 wt% hydrogen peroxide and 0.02–0.10 wt% polycarboxylate or azole inhibitor. Point-of-use dilution with 18 MΩ·cm ultrapure water ranges from 1:1 to 1:3; slurry flow on a 300 mm multi-head polisher is held at 150–250 mL/min. Typical process qualifications on 200 mm and 300 mm polishers with closed-loop endpoint detection indicate removal rates of 50–120 nm/min for TiN, 40–90 nm/min for Ti, and 1–5 nm/min for TEOS when downforce is controlled between 2.0 psi and 3.5 psi and platen/head speeds are maintained at 50–75 rpm. Selectivity to TEOS is therefore 20:1 to 60:1; this window prevents contact-level dielectric loss exceeding 20–40 Å after endpoint plus 10–20% overpolish. The liquid particle count at the point-of-use filter outlet is held below 100 particles/mL at ≥0.5 µm using a liquid particle counter calibrated to ISO 21501-4, and critical metal contamination is specified with Fe, Cu, Ni, and Cr individually below 10 ppb and total metals below 100 ppb by ICP-MS per EPA 6020B. Terminal products are tungsten contact plugs and local interconnects in DRAM, 3D NAND, and logic devices; the primary process failure mode is ring-like residual TiN at wafer edge caused by non-uniform slurry transport when pad conditioning downforce is below 3.0 lb and in situ conditioning cycles exceed 60 s intervals.

TiN Hardmask Planarization With Low-k Stop-Layer Selectivity Is Not a Drop-In Substitution

Hardmask planarization in dual damascene dielectric stacks uses TiN films to protect low-k materials during trench etch and asher strip; subsequent planarization is required before the barrier-open etch. The slurry configuration differs from W-contact clearing in that oxidizer content is reduced to 0.1–0.5 wt% hydrogen peroxide and abrasive loading after point-of-use dilution is kept at 0.5–2.0 wt% ceria or colloidal silica to preserve ultra-low-k surface chemistry. Point-of-use dilution is typically 1:2 to 1:5 with ultrapure water, and platen temperature is held at 20–25°C because TiN removal accelerates by more than 2× at process temperatures above 30°C, causing across-wafer non-uniformity. On 300 mm polishers equipped with four-zone air-bearing heads, downforce is limited to 2.0–4.0 psi and platen speed to 40–70 rpm, producing TiN removal rates of 30–80 nm/min against low-k removal of 2–8 nm/min. Endpoint is commonly controlled by motor-current change and optical interference rather than timed overpolish, because the remaining low-k thickness after etch may be 50–150 nm and overpolish beyond 20% shifts k-value by more than 0.2. Slurry pH is maintained at 4.0–5.5 (ASTM E70) to reduce dissolution of porogen-rich SiCOH films; the lower free-H₂O₂ concentration also prevents post-polish cratering. Compliance for export requires documentation under REACH Regulation 1907/2006, and although RoHS Directive 2011/65/EU applies to the finished electronic assembly, process-chemical declarations typically include bromine and chlorine content below 900 ppm to support halogen-free device requirements. Terminal products are lithographically patterned low-k dielectric stacks for advanced logic and memory back-end-of-line.

What Constraints Govern TiN Removal in Gate-Last Replacement Metal Gate Polishing?

After dummy gate removal and high-k deposition, TiN work-function layers are deposited by atomic layer deposition at thicknesses from 2 nm to 15 nm and must be polished back or left as dual-metal gate without scratching the underlying HfO₂ or Al₂O₃. The slurry after point-of-use dilution contains 0.3–1.0 wt% colloidal silica, pH 4.5–6.0 (ASTM E70), and oxidizer limited to 0.1–0.3 wt% hydrogen peroxide to achieve TiN removal rates of 20–60 nm/min and high-k removal below 1 nm/min. Point-of-use dilution is maintained in a narrow range of 1:1 to 1:2 because higher dilution suppresses the already low abrasive concentration and produces variable removal on hydrophobic high-k surfaces. Downforce is capped at 1.0–2.0 psi and platen speed at 30–50 rpm; these parameters are set after confirming that a 0.5 psi increase in downforce raises pad contact stress and increases microscratches above 5 per wafer at 0.2 µm defect inspection. Slurry particle size is controlled by dynamic light scattering per ISO 22412:2017 with D90 below 40 nm, and zeta potential is maintained above +20 mV per ISO 13099-2:2012 to prevent particle agglomeration during idle periods longer than 4 h. Experience on 300 mm gate-loop polishers shows that edge-fast polish occurs when carrier membrane backpressure falls below 0.5 psi and must be corrected by multi-zone profile adjustment; batch-to-batch removal-rate drift above 5% is typically traced to aged mixed slurry exceeding 24 h pot life. Terminal products are high-k metal gate CMOS transistors in logic and foundry nodes; leakage current after polishing is governed by residual TiN stringers and is monitored by post-polish dilute HF defect mapping.

Via-reveal manufacturing on 300 mm interposers transitions from bulk copper to a TiN diffusion barrier and then to a silicon oxide or nitride isolation liner, with via diameters commonly between 5 µm and 50 µm and via depths from 50 µm to 100 µm. The Ti/TiN slurry used after copper clearing is engineered for simultaneous barrier removal and oxide stopping; abrasive content after point-of-use dilution is 2.0–8.0 wt%, pH 3.0–4.5 (ASTM E70), and point-of-use dilution ranges from 1:1 to 1:5 with ultrapure water to balance etch rate against non-uniformity on thinned wafers. On a 300 mm via-reveal polisher with closed-loop thickness monitoring, downforce is increased to 2.5–5.0 psi and platen/head speeds to 60–100 rpm; these conditions produce TiN removal rates of 80–200 nm/min and oxide removal below 5–15 nm/min. Slurry flow is held at 200–400 mL/min because the polishing pad must clear copper debris at the barrier-open endpoint, and in-line flow meters with viscosity compensation adjusted to 1.2–3.5 mPa·s (ASTM D2196) prevent pressure oscillations that induce edge pad collapse on wafer edges. The process limitation is non-uniform clearing at large via arrays: dummy structures and sacrificial copper patterns are required to maintain pattern density between 30% and 50%, otherwise TiN clearing lag above 30 s produces copper dishing above 2 µm and oxide erosion above 1 µm across a 50 µm via. Terminal products are interposers and through-silicon via wafers for high-bandwidth memory and advanced packaging; post-polish residue control uses an SPM clean followed by dilute HF, with LPC at ≥0.5 µm below 200 particles/mL per ISO 21501-4.

Table 1 summarizes typical process windows for the downstream segments in which Ti/TiN CMP slurry is deployed. The ranges are compiled from supplier qualification reports and do not constitute a universal process specification.

TiN Structural Layer Polishing for MEMS Strain Gauges and Hard Masks

In MEMS pressure sensors and microbolometer fabrication, TiN films of 20–100 nm are deposited by reactive sputtering and polished to remove columnar grain protrusions before release etching. The slurry is point-of-use diluted at 1:5 to 1:10 with ultrapure water to reduce removal rate to 10–30 nm/min; this prevents fracture of suspended silicon nitride membranes during later dry release. Abrasive content after dilution is 0.1–0.5 wt% colloidal silica, and pH is held at 4.0–5.0 (ASTM E70) to minimize metallic contamination on exposed oxide surfaces. Downforce is set to 1.0–2.0 psi, and terminal products are pressure-sensor die, uncooled bolometer arrays, and RF-MEMS switch bodies.

If Ti/TiN Slurry Replaces Wet Etchback in Monitor Wafer Reclaim, What Defect Budget Remains Acceptable?

Blanket Ti/TiN monitor wafers and dummy wafers from PVD and CVD chambers are reclaimed by CMP where wet etchback with hydrogen peroxide/ammonia mixtures gives unacceptable front-side haze or metal carryover. Reclaim slurry is used at low point-of-use dilution of 1:0.5 to 1:1 with ultrapure water and can contain 8–15 wt% alumina or fumed silica, pH 2.5–3.5 (ASTM E70), because surface roughness after reclaim may tolerate Ra values up to 0.5–1.0 nm compared with prime device wafers at 0.1–0.2 nm. Downforce is set at 3.0–5.0 psi and platen speed at 60–100 rpm to achieve TiN removal rates of 150–400 nm/min; endpoint is determined by motor-current drop and infrared reflectivity rather than optical interference. The economic boundary is that a single reclaim pass must reduce total Ti/TiN thickness by 100–500 nm without consuming more than 1.5 L slurry per wafer; otherwise the reclaimed wafer cost exceeds a new bare silicon monitor wafer. Process compliance is less stringent than device-grade CMP, but post-polish metal contamination is still monitored by ICP-MS per EPA 6020B, and wafers exceeding 10¹¹ atoms/cm² total transition-metal surface contamination are downgraded to dummy mechanical test substrates. Terminal products are reclaimed bare silicon and oxidized silicon monitor wafers returned to ion-implant, lithography, and furnace qualification lots.

Controlling TiN Gate Electrode Topography in GaN and SiC Power Device Fabrication

In GaN high-electron-mobility transistor processing, TiN or Ti/TiN gate metallization is deposited over a Schottky gate recess and must be planarized without generating ammonia-based etch pits in the AlGaN barrier layer. The slurry is formulated with 0.5–2.0 wt% colloidal silica, pH 2.5–3.5 (ASTM E70), and hydrogen peroxide limited to 0.05–0.20 wt% because free peroxide above 0.5 wt% attacks exposed GaN surfaces and increases gate leakage after subsequent annealing. Point-of-use dilution is held at 1:1 to 1:3; downforce is limited to 1.0–2.0 psi and platen speed to 30–50 rpm, producing TiN removal rates of 15–40 nm/min and AlGaN removal below 1 nm/min. On 100 mm or 150 mm GaN-on-SiC polishers, edge exclusion is reduced to 3 mm; this is critical because GaN substrates are not available in the same wafer diameter as silicon and pad edge effects account for up to 20% yield loss if slurry flow drops below 100 mL/min. For SiC MOSFET fabrication, TiN gate electrodes may be polished back after RIE to remove residual metal stringers, but published data for this specific configuration is limited; process development must verify selectivity to underlying gate oxide and avoid creating dishing above 5 nm in 1 µm wide trenches. Compliance requires REACH 1907/2006 and, for the final device, RoHS 2011/65/EU documentation; the slurry itself is supplied as an electronic-grade chemical with total trace-metal content below 100 ppb by ICP-MS per EPA 6020B. Terminal products are GaN MMIC power amplifiers and SiC MOSFETs for automotive and industrial power modules.

DRAM MIM capacitor arrays use TiN top electrodes over ZrO₂/Al₂O₃ high-k dielectric stacks and are polished after physical vapour deposition to remove nodular growth defects and improve contact lithography depth-of-field. The slurry for this step is diluted to 1:4 to 1:8 with ultrapure water to keep removal rate at 5–20 nm/min and to prevent high-k dielectric loss below 1 nm; abrasive content after dilution is 0.3–1.0 wt% colloidal silica, and pH is maintained at 4.0–5.0 (ASTM E70). Downforce is capped at 1.0 psi to 1.5 psi, because capacitor top electrodes are often thin (10–30 nm) and overpolish directly changes capacitor area and cell capacitance. Process release criteria require removal-rate batch-to-batch variation below 3%, shear-thinning viscosity between 1.0 mPa·s and 2.5 mPa·s at 100 s⁻¹ (ASTM D2196), and post-polish LPC at ≥0.3 µm below 50 particles/mL per ISO 21501-4. The primary process conflict is residual ceria or silica abrasive trapping in high-aspect-ratio capacitor holes; therefore acidic post-polish clean with dilute HF is required, and any cleanup formulation containing amine-based additives is incompatible because it forms insoluble Ti-amine complexes that shift contact resistance. Published data for this specific configuration is limited, and initial process qualification on 300 mm wafers requires split-lot tests at 1:4, 1:6, and 1:8 dilutions before fixing the production formula. Terminal products are DRAM storage cells and embedded DRAM macros.