| HS Code | 780320 |
| Product Name | STI Polishing Slurry Electronic/EL Grade |
| Abrasive Type | Colloidal Silica |
| Mean Particle Size | 70–120 nm |
| Silica Solid Content | 30 wt% |
| Ph | 10.5–11.5 |
| Viscosity | 2–5 cP |
| Specific Gravity | 1.12–1.20 |
| Oxide Removal Rate | 2000–4000 Å/min |
| Oxide To Nitride Selectivity | >30:1 |
| Trace Metal Impurities | <1 ppb each |
| Filtration Grade | 0.2 µm |
| Shelf Life | 6 months at 15–30°C |
As an accredited STI Polishing Slurry Electronic/EL Grade factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.
| Packing | STI Polishing Slurry Electronic/EL Grade is supplied in sealed HDPE containers: 5-gallon pails and 55-gallon drums, ensuring purity. |
| Container Loading (20′ FCL) | 20′ FCL loading: STI Polishing Slurry Electronic/EL Grade packed in sealed drums on pallets, safely secured for transport. |
| Shipping | Ship STI Polishing Slurry (Electronic/EL Grade) in sealed containers, typically drums or IBC totes, to prevent contamination and evaporation. Protect from freezing and extreme temperatures. Keep containers upright, secure on pallets, and label clearly. No special hazardous material classification applies under normal shipping conditions; standard ground freight is acceptable. |
| Storage | Store STI Polishing Slurry (Electronic/EL Grade) in a tightly sealed original container in a clean, cool, dry, well-ventilated area. Maintain temperatures between 5–30°C, avoiding freezing and direct sunlight. Keep away from incompatible materials, dust, and contaminants. Do not reuse empty containers; follow manufacturer expiration and handling guidelines. |
| Shelf Life | Shelf life: 6 months from manufacture date if stored unopened at 5–25°C. Avoid freezing, agitation, and contamination. |
Shallow trench isolation planarization in sub-10-nm logic and foundry flow begins after high-density plasma or flowable chemical vapor deposition oxide fill over a 3–6 nm thermal liner and a 25–40 nm silicon nitride stop layer. The electronic/EL grade slurry is dispensed at 150–300 mL/min onto a 300-mm multi-platen rotary CMP tool, typically an Applied Materials Reflexion LK or Ebara F-REX 300, using a hard polyurethane pad with Shore D 52–58 and in-situ conditioning. Platen speed is set between 40 rpm and 90 rpm, wafer pressure between 1.0 psi and 4.5 psi, and retaining ring pressure is trimmed 0.2–0.5 psi above membrane pressure to improve edge uniformity. In this operation the slurry provides oxide removal rates of 2500–4500 Å/min on blanket TEOS wafers, while silicon nitride removal remains below 60 Å/min, producing an oxide-to-nitride selectivity above 40:1 with an adjusted additive package. High selectivity is required because the post-CMP nitride thickness on active areas must remain above 20 nm to protect the silicon substrate during subsequent wet strip. Patterned wafer non-uniformity is assessed by 49-point spectroscopic ellipsometry with a within-wafer standard deviation below 3.5%, while step-height variation across wide and narrow trenches is scanned by atomic force microscopy. Dishing in 100-µm wide shallow trench features is held below 15 nm, and edge exclusion is limited to 3 mm on 300-mm wafers. Post-polish defect density is monitored with a KLA Surfscan SP3 or SP5 dark-field inspection system; for particles larger than 0.16 µm, the count is typically less than 60 per wafer on production-grade slurry. Large particle counts are controlled by point-of-use filtration through 0.5-µm or 1.0-µm polypropylene depth filters with a fluoropolymer membrane final stage. The slurry is supplied in a recirculation loop with a low-shear magnetic drive pump, and settling is prevented by maintaining a linear flow velocity above 0.3 m/s in 3/4-inch PFA tubing. Dilution is performed only with ultrapure water meeting ASTM D5127-13 for electronic-grade water, because trace chloride, sulfate, and alkali metal ions shift zeta potential and destabilize the ceria dispersion. For logic nodes below 5 nm, post-STI step height is further reduced by a buffed second platen, where the slurry is diluted 1:1 to 1:3 with water and polished at 0.8–1.2 psi to suppress erosion of high-pattern-density regions.
In DRAM active area isolation, trench pitch falls below 40 nm, and the silicon nitride stop layer over active regions is thinned to 20–30 nm. Ceria abrasive loading is reduced to 0.2–0.6 wt% in high-selectivity electronic-grade grades to minimize nitride loss during overpolish. Oxide removal rate on HDP oxide is maintained at 1800–3200 Å/min, while nitride removal rate is suppressed to 15–40 Å/min, yielding blanket selectivity between 50:1 and 120:1 depending on additive concentration and pH. The dominant process conflict is cell-to-periphery pattern density mismatch; the array may have 45–55% trench density, while peripheral circuitry densities are often below 10%. Such mismatch produces localized overpolish at array edges unless the CMP tool uses multi-zone head pressure control. Production tools such as the Ebara F-REX 300 with 7-zone membrane control and real-time optical endpoint are used to trim center and edge zones independently. Motor current endpoint detection is affected by pad temperature and slurry solids content; therefore optical endpoint monitoring of nitride removal is preferred. Post-CMP measurements on DRAM STI wafers include atomic force microscopy line scans across 32 lines at the array boundary; oxide loss at the array edge must be below 8 nm after selective nitride strip. Slurry particles are measured by single-particle optical sensing per SEMI C63-0218; the concentration of particles above 0.2 µm is held below 10,000 per mL in the day tank. Point-of-use filtration uses a 0.5-µm nylon or PVDF membrane capsule, and the dispense line is purged with nitrogen after idle periods longer than 15 minutes. If idle time exceeds 2 hours, the slurry is recirculated through the filter loop at 10–20 L/min to shear and redisperse loose agglomerates. Slurry pH is kept within ±0.2 pH units of the specified value, measured by an inline pH probe with automatic temperature compensation; excursion beyond that range changes ceria zeta potential and increases particle adhesion to nitride surfaces.
In 200-mm BCD and discrete power technologies, the STI module must planarize a thicker high-density plasma oxide fill, commonly 450–700 nm, deposited over a 20–40 nm silicon nitride stop layer. The thicker fill increases total polish time and pad temperature, and the wider active-area openings in DMOS regions create large exposed nitride areas where erosion must be limited. A medium-selectivity electronic-grade STI slurry is often selected, with oxide removal rates of 3000–5500 Å/min on blanket HDP oxide and nitride removal rates of 40–80 Å/min. On a 200-mm CMP tool using a dual-stack platen, the main polish is performed at 3.0–5.0 psi downforce and 35–70 rpm platen speed, followed by a low-pressure buff at 1.0–2.0 psi to reduce process-induced defects. Pad surface temperature is monitored by infrared sensor; if pad temperature exceeds 60 °C, ceria particle aggregation and pad glazing have been observed, leading to a non-uniform removal profile with center-to-edge range above 10%. This is controlled by increasing slurry flow from 150 mL/min to 250 mL/min and adjusting conditioner downforce. Post-CMP nitride thickness is measured on five dies per wafer by spectroscopic ellipsometry; the minimum nitride remaining on large DMOS active regions must be above 30 nm before hot phosphoric acid strip. The oxide-to-nitride selectivity is intentionally lower than in advanced logic because the thicker nitride layer tolerates some loss, and excessive selectivity can trap slurry particles in high-topography regions due to reduced mechanical action. Slurry cleanliness follows electronic-grade requirements: sodium, potassium, iron, and aluminum are each below 10 ppb by ICP-MS after digestion, and total transition metal content is below 1 ppm. The slurry is incompatible with stainless steel pump heads; wetted components are specified as polytetrafluoroethylene, perfluoroalkoxy alkane, or polypropylene. Hard plumbed lines are flushed with ultrapure water after each lot, and the point-of-use filter is replaced after 48 hours of continuous polishing or when line pressure differential exceeds 0.15 MPa.
In 3D NAND memory fabs, the peripheral CMOS region requires STI-like isolation to separate page buffer, charge pump, and row decoder transistors, while the array region is occupied by stacked wordline layers and slit trenches. The oxide fill in the periphery is typically a flowable CVD oxide or TEOS/O3 film over a silicon nitride stop layer; electronic/EL grade ceria slurry is used on the same 300-mm CMP platforms as logic, but with a different endpoint strategy. Whereas logic wafers are polished to an open nitride surface, 3D NAND peripheral polish often stops in the oxide overburden before exposing nitride to avoid slurry attack on slot contacts. This requires lower removal rate and improved within-wafer control; oxide removal rates of 1500–2500 Å/min are common, with within-wafer non-uniformity below 4% at 3-mm edge exclusion. The slurry must be free of particles larger than 0.5 µm because these can embed in the exposed oxide surface and become polysilicon gate defects after subsequent etching. Post-polish dark-field inspection with a KLA 29xx broadband plasma tool is used to classify defects; on a clean 300-mm wafer, defect density of particles greater than 0.10 µm is held below 0.04 defects/cm². Large particle count in the slurry is reduced by a two-stage filtration: a 1.0-µm polytetrafluoroethylene membrane primary filter followed by a 0.2-µm polypropylene capsule at the dispense point. The risk of ceria residue in array slit regions is mitigated by a dedicated buff step with a non-abrasive or ultra-diluted slurry, followed by an aqueous ammonia/hydrogen peroxide cleaning sequence. Alkaline post-CMP cleaning with dilute ammonia-peroxide mixture at pH 9–10 and megasonic energy is used to remove residual ceria particles from hydrophobic oxide surfaces. Slurry pH is monitored inline and maintained within a tighter band of ±0.15 pH units for 3D NAND applications because flowable oxide has higher silanol density and is more susceptible to particle adhesion.
| Segment | Tool platform | Downforce (psi) | Platen speed (rpm) | Oxide removal rate (Å/min) | Nitride removal rate (Å/min) | Selectivity ratio |
|---|---|---|---|---|---|---|
| Logic/foundry sub-10 nm | Reflexion LK / F-REX 300 | 1.0–4.5 | 40–90 | 2500–4500 | 20–60 | 40:1–120:1 |
| DRAM sub-40-nm half-pitch | Ebara F-REX 300 | 1.5–3.5 | 40–80 | 1800–3200 | 15–40 | 50:1–120:1 |
| BCD/power 200-mm | Dual-stack rotary | 3.0–5.0 | 35–70 | 3000–5500 | 40–80 | 30:1–70:1 |
| 3D NAND periphery | 300-mm multi-platen | 1.0–2.5 | 30–60 | 1500–2500 | 10–35 | 40:1–100:1 |
Frontside-illuminated CMOS image sensor flows at 90–65 nm nodes use shallow trench isolation to separate pinned photodiodes and adjacent transfer-gate structures. The STI depth is relatively shallow at 200–300 nm, and the nitride stop layer is thinner than in logic, requiring low-shear polishing to avoid silicon lattice damage near the photodiode surface. Electronic/EL grade slurry for this application is specified with iron, nickel, and copper each below 5 ppb by ICP-MS because transition metal contamination increases dark current and white pixel defect density. The polishing process runs at low downforce of 1.0–2.5 psi on 200-mm or 300-mm tools, with oxide removal rates between 1200 Å/min and 2500 Å/min and nitride removal below 30 Å/min. A key operational boundary is the prevention of slurry agglomeration at the point of use; even short periods of stagnation can form loose aggregates that are not captured by the 0.5-µm point-of-use filter and subsequently transfer to the wafer as larger soft defects. Post-CMP cleaning uses dilute hydrofluoric acid followed by ammonium hydroxide/hydrogen peroxide megasonic cleaning to remove ceria residuals without eroding the thin nitride or damaging the silicon surface. Published data for this specific configuration is limited; however, fabs commonly extend the STI slurry qualification by adding continuous particle counting on the delivery loop and wetting the pad with the slurry for at least 10 minutes before the first wafer. Defect inspection is performed with dark-field wafer scanners at 0.12 µm threshold, and a single large defect in the pixel array can require lot reprocessing. The slurry is therefore recirculated through an inline optical particle counter and a zeta potential sampling loop; zeta potential is measured according to ISO 13099-1:2012 and maintained within the narrow range specified for the particular additive package.
| Parameter | Test method or equipment | Typical control limit |
|---|---|---|
| Particle count >0.2 µm | SEMI C63-0218 single-particle optical sensing | <10,000 per mL |
| Large particles >0.5 µm | Optical particle counter in point-of-use loop | <500 per mL |
| Sodium, potassium, iron, aluminum | ICP-MS after acid digestion | <10 ppb each |
| Transition metals total | ICP-MS per EPA 6020B | <1 ppm |
| pH control band | Inline pH probe with ATC | ±0.15–0.2 pH units |
| Zeta potential stability | ISO 13099-1:2012 | Product-specific narrow band |
| Wafer defects >0.16 µm | KLA Surfscan SP3/SP5 dark-field inspection | <60 per wafer |
| Dilution water quality | ASTM D5127-13 | Electronic-grade ultrapure water |
Silicon photonic integrated circuits on 200-mm SOI substrates use shallow etched trenches filled with oxide for waveguide sidewall passivation and electrical isolation. The ceria slurry is applied only when the fill oxide must be planarized without damaging the 220-nm silicon device layer beneath a 15–25 nm nitride stop layer. A low-downforce process of 1.0–1.5 psi is used, and endpoint is determined by optical thickness monitoring. For this niche configuration, published data is limited, and process qualification typically proceeds through pilot-lot defectivity trials.
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STI Polishing Slurry Electronic/EL Grade is a high-purity aqueous dispersion for chemical-mechanical planarization and final polishing of electronic substrates. The Electronic/EL Grade designation identifies the low-alkali, low-halide variant used where mobile-ion contamination and post-CMP residue defects are yield-limiting. The product is controlled for solids content, particle size distribution, zeta potential, pH, specific gravity, large particle count, and trace metal content. In front-end semiconductor processing, the grade is specified for interlayer dielectric planarization, shallow trench isolation oxide polish, copper barrier clearing, silicon final polish, and compound semiconductor surface conditioning. Typical electronic-grade colloidal silica slurries in this class are supplied with solids loadings of 20 wt% to 40 wt% and volume-median particle sizes below 100 nm. Published lot-specific data for the STI Electronic/EL Grade is limited; therefore, process qualification should verify the product against the end-user’s post-polish defect inspection protocol and required film removal uniformity.
The product specification framework includes solids content, specific gravity, pH, median particle diameter, particle size span, large particle count, and trace impurity concentrations. Solids content determines abrasive concentration and removal rate under a given downforce and table speed. Specific gravity provides a rapid in-line check for concentration drift. pH controls removal chemistry and colloidal stability. Median particle diameter and size distribution width control surface roughness and agglomerate formation probability. Large particle counts at the 0.5 µm threshold are monitored because only a small number of oversized particles can produce scratches on high-density patterned wafers. Trace metal and anion concentrations are controlled to prevent mobile-ion contamination and post-clean residue.
Optical-grade slurries are often released for stock removal rate and surface figure control, with less restrictive limits on sodium, potassium, aluminium, iron, copper, chloride, and sulfate. In front-end semiconductor applications, those species persist after clean, diffuse during later thermal treatments, or precipitate as charged defects at oxide interfaces. The Electronic/EL Grade is therefore differentiated by analytical release criteria and packaging hygiene rather than by the abrasive mechanism alone.
Compared with fumed silica slurries, colloidal silica electronic-grade slurries generally exhibit a tighter particle size distribution and a lower tendency to form hard agglomerates, but they may require tighter ionic strength control. Compared with ceria-based slurries, electronic-grade silica provides lower blanket oxide removal rates but usually offers improved oxide-to-nitride selectivity and simpler post-CMP cleaning because the abrasive is silica rather than ceria. The STI Electronic/EL Grade is selected where cleanability, mobile-ion control, and selectivity are more important than maximum oxide stock removal.
The Electronic/EL Grade differs from general engineering polishing slurries by the absence of high levels of suspension aids, surfactants, or colorants. That additive restriction reduces organic residue on surfaces undergoing subsequent CVD, PVD, or lithography adhesion steps. It also reduces foam formation in day-tank loops, which is a common operational problem with surfactant-containing polishing compounds.
| Attribute | Electronic/EL control basis | Optical-grade control basis | Test method designation |
|---|---|---|---|
| Sodium | < 1 mg/kg | 10–100 mg/kg | ASTM D5673-16 |
| Chloride | < 5 mg/kg | 50–500 mg/kg | ASTM D512-12 |
| Large particle count ≥ 0.5 µm | < 100 counts/mL | 1,000–10,000 counts/mL | ASTM F661 |
| Lot-to-lot pH variation | ± 0.2 | ± 0.5 | ASTM E70 |
The control bases in the table are representative of electronic-grade CMP slurry specifications rather than vendor-specific lot limits. A supplier certificate of analysis should still be checked for the specific STI lot.
In a 300 mm copper damascene line, the Electronic/EL Grade slurry is introduced at the bulk copper polish step or at the barrier-clearing step depending on the integration scheme. In both positions, the slurry is distributed through a day-tank loop to multiple polishing heads. Point-of-use flow rates commonly range from 100 mL/min to 400 mL/min per head. The slurry must remain colloidally stable under recirculation and must not generate large particle counts during intermittent flow. Polishers with platen temperature control at 25 °C to 35 °C are preferred because elevated storage or loop temperature accelerates particle aggregation and microbial growth. When slurry lines are idle, the material should not be allowed to dry in the dispense nozzle because abrasive crusts can break free and create scratches.
For oxide interlayer dielectric and shallow trench isolation oxide, the slurry is used with polyurethane pads and conditioning disks. The process window for oxide CMP generally falls between 2 psi and 6 psi downforce and table speeds of 30 rpm to 90 rpm. Within this range, the slurry should maintain removal rate uniformity and keep nonuniformity below the integration-imposed limit, typically measured by high-resolution film thickness mapping after polishing. Published data for the STI Electronic/EL Grade on specific pattern densities is limited, so removal-rate selectivity and dishing magnitude must be generated on the end-user’s target patterned wafers.
For silicon final polishing, the Electronic/EL Grade is used at low downforce to remove sub-surface damage while minimizing haze. For barrier clearing, the slurry is paired with a barrier-selective step that maintains low dishing and erosion on low-k dielectrics. In each case, colloidal stability and low metal impurity content are necessary but not sufficient for process acceptance; interaction with the pad, conditioning disk, and post-CMP clean must be optimized on the production tool.
Batch-to-batch variability in slurry lots is typically assessed by a short-loop polish on blanket wafers. This test measures dielectric film removal, surface roughness, and defectivity. The short-loop avoids consuming patterned device wafers and is used to release lots into the fab slurry distribution system. In most cases, a new lot is acceptable only when its blanket removal rate falls within the internal control range, usually a relative deviation of no more than 5% from the baseline, and its large particle count is below the fab alarm level.
The Preston equation describes removal rate as the product of downforce and relative velocity, but CMP systems frequently depart from Prestonian linearity above 5 psi downforce or below approximately 50 mL/min slurry delivery. In that regime, pad-wafer contact changes from a mixed-lubrication mode toward direct contact, and removal becomes sensitive to local pH depletion, pad glazing, and particle starvation. For an Electronic/EL Grade slurry, the non-Prestonian transition is significant because defects can increase even when blanket removal rate remains acceptable.
On a multi-head rotary polisher with a platen diameter near 750 mm, edge-to-center slurry distribution from a single dispense point can produce differences in effective solids concentration. Condensation, rinse-water carryover, and low dispense flow can reduce slurry pH while increasing the concentration of dissolved species. Batch-to-batch variation in the slurry’s buffering capacity then appears as within-wafer nonuniformity and edge-defect drift. Process monitoring should therefore include removal rate, within-wafer nonuniformity, edge exclusion zone defect density, and large particle count trends instead of blanket removal rate alone.
Pad conditioning disk choice influences the non-Prestonian threshold. Fine diamond conditioners that create a dense micro-texture tend to support a thicker slurry film and delay direct pad-wafer contact. Coarse conditioners increase removal rate but also increase local pressure variation and defect probability. For Electronic/EL Grade slurries, removal rate and defect density should be mapped as a function of downforce, table speed, slurry flow, and pad conditioning frequency. A central composite experimental design is often used for process window optimization, with blanket oxide removal rate, within-wafer nonuniformity, and scratch count as responses.
After polishing, the Electronic/EL Grade slurry must be cleared by the post-CMP clean sequence. Residual colloidal silica that is not removed by scrubbing or megasonic cleaning can remain as a sub-monolayer film and appears as localized light-scattering defects. The slurry’s zeta potential determines whether particles remain electrostatically repelled or adsorb onto oxide, copper, or barrier materials. For silica dispersions above pH 10, zeta potentials in the −30 mV to −50 mV range are typical and provide electrostatic stabilization against agglomeration. If carbon dioxide ingress lowers pH below 9, the surface charge can fall toward the isoelectric point, promoting aggregation and increasing the risk of filter clogging and polish defects.
Post-CMP cleaning compatibility is also assessed by residual cation measurement rather than visual inspection alone. Wafers polished with the Electronic/EL Grade slurry are evaluated for sodium, potassium, aluminium, iron, copper, and chloride residues after cleaning. A robust process shows no statistically significant shift in residual metal levels compared to the established baseline. This is important because trace metal residues contribute to mobile charge, interface state density, and device reliability drift.
Electronic/EL Grade slurry is typically filtered at point-of-use through depth filters or pleated polypropylene cartridges rated from 0.5 µm to 5 µm. The selected filter must not release collected solids during pressure surges. A sharp increase in large particle counts after filter replacement can indicate hydraulic shock or an uncompensated bypass. Large particle count at sizes ≥ 0.5 µm should be trended each lot because only a small number of oversized particles can produce scratches on dense patterned wafers.
| Control point | Analytical method | Verification target |
|---|---|---|
| Volume-median particle size | ISO 22412:2017 | Lot release within vendor-defined range |
| pH | ASTM E70 | Recorded at 25 °C |
| Specific gravity | ASTM D4052 | Lot conformance |
| Trace metals | ASTM D5673-16 | Front-end impurity limits |
| Large particle count | ASTM F661 | Trended against control chart |
| Cleanroom packaging | ISO 14644-1:2015 | Class 5 or better |
The verification targets in this matrix are typical quality-control points for electronic-grade CMP slurry release. Actual STI lot limits, pad types, and defect thresholds should be obtained from the supplier certificate of analysis and the fab integration specification.
Colloidal silica suspensions depend on particle surface charge for stability. In the pH 10 to 11 range, the silica surface is negatively charged, and electrostatic repulsion prevents flocculation. Carbon dioxide absorbed from air shifts the carbonate equilibrium and lowers pH, moving the dispersion toward the isoelectric point and increasing the probability of aggregate formation. The Electronic/EL Grade should therefore be stored in closed containers with minimal headspace exchange. If day-tank loops are open to ambient air, pH should be measured at the start of each shift and before lot changes. A downward pH trend of more than 0.2 in 24 h indicates either carbon dioxide ingress or contamination by acidic rinse water.
Zeta potential can be tracked by electrophoretic light scattering according to ISO 13099-1:2012, with a typical alarm threshold below −30 mV for oxide CMP. When zeta potential drifts toward zero, the probability of particle agglomeration and scratch defect formation increases even before the large particle count exceeds the control limit.
For slurry qualification, the Electronic/EL Grade should also be evaluated after any transportation segment that includes unheated zones. Freezing can irreversibly aggregate silica. Prolonged storage above 35 °C can accelerate pH drift, microbial growth, and particle size enlargement. Containers should remain sealed to limit carbon dioxide uptake, which lowers pH and reduces electrostatic stabilization. If settling is observed in drums or totes, gentle recirculation should be used before drawing into the distribution loop. Aggressive agitation can create foam and microbubble defects at point-of-use.
Because the Electronic/EL Grade is used in front-end semiconductor processes, waste streams containing the slurry must be handled according to site effluent limits for suspended solids, pH, and trace metals. The material should not be mixed with ammonia-peroxide or sulfuric-peroxide cleaning baths unless the treatment system is specifically designed for the resulting effluent chemistry and pH neutralisation.
