In front-end silicon wafer fabrication, electronic/EL-grade SiN/SiO etchant is integrated into pre-furnace wet bench sequences, where the chemistry removes sacrificial thermal silicon dioxide from active region surfaces before gate oxidation or epitaxial growth. The standard working bath is prepared by mixing 40 wt% ammonium fluoride solution and 49 wt% hydrofluoric acid in a 7:1 volume ratio, then filtering through a 0.05 µm PTFE membrane under constant recirculation. Bath temperature is held at 22–25 °C with a temperature control band of ±0.5 °C, and immersion time is adjusted from 45 s to 180 s depending on oxide thickness and device node. Under these conditions, thermal oxide etch rate on <100> silicon monitor wafers is 80–120 nm/min as measured by spectroscopic ellipsometry, while LPCVD silicon nitride removal remains below 1 nm/min. This selectivity allows sacrificial oxide removal without consuming nitride spacers, pad layers, or hard masks. Metallic impurity control is implemented at the raw-material level: the HF component is purchased to SEMI C28 electronic-grade limits, and the NH₄F component is controlled to SEMI C10 ammonium fluoride requirements, with sodium, potassium, iron, copper, chromium, zinc, and calcium each held below 10 µg/L by ICP-MS. Bath aging is monitored by dissolved silicon concentration, because the conversion of HF to hexafluorosilicic acid at 15–20 g/L silicon can reduce oxide etch rate by 30–50% and elevate surface microroughness beyond the 0.3 nm RMS limit measured by AFM on 300 mm monitor wafers. Equipment-wetted parts are PFA and PTFE only, and recirculating particle counts are maintained below 25 particles/mL at 0.2 µm sizing to prevent yield loss from particle-induced gate oxide defects. After etch, the wafers move into quick dump rinse and then into overflow rinse with 18 MΩ·cm ultrapure water meeting ASTM D5127; the cleaned wafers subsequently enter gate oxidation, diffusion, or epitaxial growth steps and are processed into logic, DRAM, NAND flash, and analog integrated circuits.

What Process Window Governs Sacrificial Oxide Release in MEMS Cavities?

Sacrificial oxide release in surface-micromachined MEMS devices is performed with buffered SiN/SiO etchant formulations where the objective is complete removal of 0.5–2.0 µm of phosphosilicate glass or undoped silicon dioxide without dissolving low-stress silicon nitride structural films. In 7:1 BOE at 22–25 °C, thermal oxide etches at 80–120 nm/min, but PECVD silicon nitride deposited at 300–400 °C may lose 1–3 nm/min because hydrogen-rich Si–N and Si–H bonds are more susceptible to fluoride attack than LPCVD nitride. For a 2 µm sacrificial oxide layer, the calculated immersion interval is 17–25 min, with an additional 5–10 min overetch to compensate for transport-limited etching in 2–5 µm-wide release trenches and under 1–2 µm-thick polysilicon beams. The wet bench is configured with Teflon cassettes, continuous 0.05 µm PTFE bath recirculation, and a nitrogen purge across the freeboard; no ultrasonic or megasonic agitation is used during release because acoustic energy can fracture compliant beams with critical dimensions below 2 µm. Etch rate decay is monitored every 30 min by test coupon measurement and by active HF titration, since dissolved silicon at 2 g/L can reduce the etch rate by 10–15% in confined cavities. After release, the wafers are transferred to 18 MΩ·cm ultrapure water overflow rinse for 10–15 min, then to isopropanol vapor drying or supercritical CO₂ drying at 10–20 MPa and 35–45 °C to avoid capillary-force stiction. Incomplete oxide removal is detected by optical interferometry of cantilever deflection, and nitride loss is measured by AFM step height on test structures; this sequence supports production of inertial sensors, microbolometers, RF switches, and microfluidic membranes.

Crystalline silicon photovoltaic production consumes SiN/SiO etchants primarily for edge junction isolation after phosphorus diffusion and for rework of PECVD silicon nitride anti-reflective coatings after inline optical inspection. Front-side PECVD SiN:H layers of 70–90 nm are stripped in horizontal inline tools with HF concentration between 5 wt% and 15 wt% at 18–25 °C, using immersion or spray times of 60–180 s. Because the etch removes silicon nitride faster than the underlying silicon oxide passivation on textured surfaces, endpoint control is based on color uniformity, weighted reflectance, and sheet resistance measured by four-point probe; silicon consumption of more than 20 nm from the emitter is considered non-conforming because it shifts sheet resistance and may create shunting paths. Texture morphology influences local etch rate: wafers with 8–15 µm pyramid texture consume etchant non-uniformly at pyramid tips, and inline agitation by bubble or roller assist is adjusted to reduce tip rounding. Bath life in photovoltaic fabs is shorter than in microelectronics because dissolved silicon loadings rise quickly; active HF is determined by fluoride ion selective electrode and hydroxide titration, and the bath is replenished or replaced when dissolved silicon exceeds 10–15 g/L. Exhausted baths containing hexafluorosilicic acid are neutralized with calcium hydroxide and filtered through 5 µm bag filters before discharge, consistent with local wastewater permits and site environmental management plans. Outputs include mono-PERC, TOPCon, and heterojunction solar cells, where the etchant is also used to condition the rear-side dielectric stack before screen-printed metallization.

Contact Hole Cleaning in TFT-LCD Arrays Without Indium-Tin-Oxide Attack

Horizontal spray equipment in thin-film transistor liquid crystal display array fabs meters electronic/EL-grade SiN/SiO etchant across Gen 8.5 and Gen 10.5 glass substrates for contact hole residue removal after reactive ion etching of silicon nitride and silicon oxide passivation layers. The chemistry is diluted to 0.5–2 wt% HF with temperature maintained at 23 ± 1 °C, conveyor speed set to 1.0–2.5 m/min, and oscillating nozzle manifolds operated at 0.5–1.0 Hz to prevent droplet patterning. Because HF aggressively dissolves indium tin oxide, open ITO pads are protected by photoresist or processed in split-flow chambers where the etchant contacts only the array-facing side; ITO thickness loss is checked by four-point probe sheet resistance shift and must remain below 5% of the 70–90 nm transparent electrode film. Silicon nitride and silicon oxide etch rates on blanket test coupons are measured by spectroscopic ellipsometry before production lots are released, and via-chain contact resistance is tested after subsequent molybdenum or aluminum deposition. Recirculated etchant is filtered through 0.2 µm PTFE cartridges, with particle counts kept below 10 particles/mL at 0.2 µm sizing, because particle deposition on 4K and 8K panels creates bright pixel defects and reduces panel-grade yield. Bath temperature, acid concentration, and dissolved metal concentrations are logged continuously; copper, iron, and zinc are held below 5 µg/L to prevent lateral leakage and photoconduction anomalies in a-Si or oxide TFT backplanes. Interlocks are arranged in accordance with SEMI S2 equipment safety guidelines, and acid exhaust scrubbers maintain stack HF concentrations below 1 ppm. The resulting backplanes are used in high-resolution LCD and OLED panels, where the etch step is followed by dry resist strip, hot DI water cascade rinse, and hot air knife drying before vacuum deposition of the next electrode layer.

During the backside processing of high-brightness gallium nitride LEDs, buffered SiN/SiO etchants remove via-bottom silicon dioxide after laser lift-off and before n-contact metallization. The process window is constrained by the requirement to clear 100–200 nm of PECVD silicon dioxide without roughening the exposed n-GaN surface or attacking exposed chromium/gold metal layers; therefore NH₄F/HF ratios of 10:1 or higher are selected and immersion is limited to 30–60 s at 20–25 °C. Under these conditions the PECVD silicon dioxide etch rate is 40–80 nm/min, while GaN etch rate remains below the 0.5 nm/min detection limit by AFM step-height analysis after 5 min exposure, allowing complete oxide removal without measurable pit formation. The wafers are rinsed in 18 MΩ·cm ultrapure water, spin-dried under nitrogen, and transferred under controlled humidity below 40% RH to electron-beam evaporation for Ti/Al/Ni/Au contact metallization. Transfer length method structures with 100 µm spacing are used to verify contact resistance; values above 1 × 10⁻⁴ Ω·cm² are attributed to residual oxygen or fluorine contamination and trigger re-cleaning or argon plasma surface conditioning. Finished devices include high-power LED chips for general lighting, automotive headlamps, and micro-LED display arrays, where yield loss from surface pitting is monitored by wafer-level photoluminescence and dark-field inspection.

When Interconnect Redistribution Requires Pad Surface Conditioning Before Wire Bonding

Wafer-level packaging and redistribution layer processing use SiN/SiO etchants to condition aluminum and copper bond pad surfaces after final passivation opening, where the goal is removal of 5–20 nm of pad oxide and post-etch silicon nitride or silicon oxide residue without dissolving the underlying interconnect metal. Single-wafer puddle or spray tools apply the etchant with HF concentration of 0.5–1.0 wt% at 25–30 °C for 20–60 s, with wafer rotation between 300 rpm and 800 rpm to provide uniform liquid film thickness. Because dissolved copper in shared baths can redeposit on aluminum pads, separate dedicated etching modules are assigned to copper-bearing wafers; otherwise copper contamination above 1 × 10¹⁰ atoms/cm² is detected by TXRF and causes wire bond lift failures. Surface conditioning is verified by XPS survey scans showing metallic aluminum or copper peaks with oxygen content below 15 at.%, and by ellipsometry on monitor wafers confirming removal of Si–O and Si–N films. After etching, the wafers are rinsed, nitrogen-dried, and transferred to electroless nickel electroless palladium immersion gold plating or directly to wire bonding within 2–4 h to limit native oxide regrowth. End-use devices include fan-out wafer-level packages, system-in-package modules, and 2.5D interposer devices, where pull testing of 25 µm gold wire bonds at 5–8 g force is used to confirm bonding consistency after pad conditioning.