Shallow trench isolation planarization at logic nodes below 28 nm terminates with a silicon nitride clearing operation in which an electronic-grade slurry removes the stop layer from active moat regions while suppressing oxide loss in STI fill. The slurry is a colloidal silica dispersion with D50 particle size between 30 nm and 50 nm, solid content of 5 wt% to 10 wt%, and pH 9.0 to 10.5 measured per ASTM E70-19. Point-of-use dilution with ultrapure water is maintained at 1:1 to 1:3 after 0.1 µm point-of-use filtration. On a 300 mm wafer polisher with a polyurethane IC1000 pad, typical process settings include carrier downforce 2.5 psi to 4.0 psi, platen speed 60 rpm to 90 rpm, head speed 57 rpm to 87 rpm, and slurry flow 200 mL/min to 300 mL/min. The slurry displays silicon nitride removal rates in the 400 Å/min to 800 Å/min range and silicon nitride-to-high-density plasma oxide selectivity from 8:1 to 20:1, depending on additive packing. In situ endpoint is obtained from optical emission or platen motor current, and over-polish is limited to 10% of endpoint time to avoid nitride pitting and pad glazing. Particle defect density on blanket nitride is monitored with a KLA Surfscan SP2-type scanner, with post-polish adders above 0.12 µm held below 50 per wafer. Slurry pH drift above 10.5 induces shear-induced agglomeration of colloidal silica, increasing microscratches and ring defects; recirculation loops must use low-shear bellows pumps and 0.5 µm depth filtration to preserve dispersion stability. The terminal film stack typically leaves 5 nm to 10 nm of pad oxide intact, and nonuniformity across the wafer is maintained below 5% at 1σ. The slurry should not be blended with acidic post-CMP cleaning residues because pH below 7.0 destabilizes the dispersion and produces gel formation in the pad grooves. Metal impurity acceptance for this electronic-grade material is commonly specified at less than 1 ppm total chromium, iron, nickel, and copper, based on inductively coupled plasma mass spectrometry after acid digestion, with mobile ions sodium and potassium limited to 100 ppb each for gate stack compatibility.

What Process Window Is Required When a Nitride Slurry Serves as a Sacrificial Hard Mask Removal Fluid in 3D NAND Staircase Modules?

In 3D NAND staircase formation, silicon nitride hard masks with thicknesses of 200 nm to 800 nm are deposited over the alternating stack before staircase etch; subsequent oxide fill of the etched terrace structure creates local topography that must be planarized without rounding the nitride-defined step corners. The electronic-grade slurry in this application is diluted more aggressively, typically 1:4 to 1:6 with ultrapure water, because high solid loading at the 1:1 dilution used in STI produces excessive nitride recess across terraces. Operating pH is held at 9.0 to 9.8 to reduce oxide filler loss while maintaining nitride removal rates of 300 Å/min to 600 Å/min. A dual-layer pad stack comprising a hard polyurethane top pad and a conformable sub-pad is used on a multi-zone carrier at downforce 2.0 psi to 3.5 psi. Platen speed is set between 50 rpm and 70 rpm, and slurry flow is reduced to 150 mL/min to 200 mL/min because thinner slurry films improve step-height reduction efficiency. Selectivity to plasma-enhanced tetraethyl orthosilicate oxide is maintained above 4:1, but over-polish beyond 15% can cause terrace edge rounding and local nitride breakthrough at die edge, leading to stringer defects in downstream tungsten replacement. In-situ pad conditioning is performed with a diamond disk at 0.5 psi conditioning force after every wafer to keep the pad surface from glazing due to the low water content of the diluted slurry. Post-polish cleaning with dilute ammonium hydroxide at pH 10 removes colloidal silica residue from nitride terraces without attacking the underlying oxide fill; megasonic energy above 40 W is avoided because it causes cavitation damage at the terrace step edges. A production lot is typically rejected if within-wafer step-height nonuniformity exceeds 6% at 1σ or if adders above 0.09 µm exceed 100 per wafer on a 300 mm blanket monitor. Rheological data for the diluted slurry show viscosity between 1.0 mPa·s and 1.3 mPa·s at 25 °C, which allows stable point-of-use distribution through 1/2 in PFA tubing without sedimentation. Because the staircase process exposes multiple alternating dielectric stacks, the slurry must have 0.01 wt% maximum non-volatile residue after drying to avoid drying-induced defects during queue time. The terminal result is a planar oxide staircase with intact nitride hard mask gates, ready for selective nitride stripping in hot phosphoric acid.

On 150 mm GaN-on-SiC high-electron-mobility transistor wafers, silicon nitride passivation layers deposited by plasma-enhanced chemical vapor deposition at 100 nm to 200 nm thickness are polished to reduce trench topography before field-plate metallization. The electronic-grade slurry used for this operation is a low-solids colloidal silica dispersion with D90 particle size below 70 nm, total metal contamination under 50 ppb, and alkali metal concentration under 10 ppb, because sodium and potassium introduced at the nitride surface degrade gate leakage current and cause surface trap formation. Particle size is verified by dynamic light scattering per ISO 22412:2017, and cleanliness of the polishing bay is maintained to ISO 14644-1:2015 Class 4. The slurry is diluted 1:3 to 1:5 with point-of-use ultrapure water and maintained at pH 8.5 to 9.5; the upper pH limit is tighter than in silicon CMOS because GaN surfaces in exposed field areas are attacked above pH 10 under frictional heating. Polishing is performed on a single-wafer CMP tool with a sub-1 psi carrier backpressure, downforce 1.0 psi to 2.0 psi, platen speed 40 rpm to 60 rpm, and slurry flow 120 mL/min to 180 mL/min. Silicon nitride removal rate is typically limited to 250 Å/min to 450 Å/min to avoid nitrogen vacancy generation at the nitride/GaN interface. Surface roughness after polishing is evaluated by tapping-mode atomic force microscopy over 5 µm × 5 µm scans, with root mean square roughness held below 0.5 nm. Defect inspection on a KLA Candela-type tool or equivalent dark-field scattering system counts post-polish adders above 0.08 µm; production acceptance is usually below 30 adders per wafer. The slurry must be filtered through 0.1 µm point-of-use filtration to prevent large-particle agglomerates from creating microscratches that run along the GaN [11-20] direction. A post-polish rinse with dilute citric acid solution at pH 4 is used to remove trace metals without etching the silicon nitride; however, citric acid left on the wafer longer than 120 s can chelate aluminum from the nucleation layer and form pit defects. Batch-to-batch pH drift must be held below 0.2 pH units over 24 h because the passivation layer is thin and polish rates shift 8% per 0.1 pH unit change. Published data for the exact pH-dependent removal rate on GaN-specific nitride stacks remains limited, so process development should use a blanket nitride monitor wafer and an electrochemical copper-free polish cell before committing a production lot.

If Copper Redistribution Layers Are Exposed during Silicon Nitride Passivation Polishing in Fan-Out Wafer-Level Packaging, Which Corrosion and Selectivity Controls Apply?

In fan-out wafer-level packaging, silicon nitride passivation films 200 nm to 1000 nm thick are deposited over copper redistribution layers and then polished to planarize the overburden before polymer curing and solder mask application. When the copper surface is exposed during the final polish phase, the slurry must contain a corrosion inhibitor to prevent copper dissolution and dishing. Benzotriazole or a substituted triazole derivative is added at 0.05 wt% to 0.2 wt%; below this range copper removal can exceed 5 Å/min and generate etch pits, while above this range the inhibitor can passivate the silicon nitride surface and reduce nitride removal rate to below 150 Å/min. Slurry pH is set between 9.0 and 9.8 to balance silica suspension stability and copper oxide dissolution. Point-of-use dilution is 1:2 to 1:4; a higher water fraction reduces pad temperature rise, which is critical because pad temperature above 45 °C accelerates copper corrosion and shortens pad life. Process settings on a 300 mm CMP tool include downforce 2.0 psi to 3.0 psi, platen speed 50 rpm to 80 rpm, head speed 48 rpm to 78 rpm, and slurry flow 180 mL/min to 250 mL/min. In this configuration silicon nitride removal rate is maintained between 400 Å/min and 700 Å/min, while copper removal rate is suppressed below 1 Å/min on a blanket copper wafer after a 60 s dynamic polish. Electrochemical impedance spectroscopy on a rotating disk electrode is used to verify passivation film resistance above 10 kΩ·cm² in the diluted slurry. The slurry must not be mixed with amine-based cleaning agents because amine coordination with copper increases dissolution at pH above 10 and produces organic residues on the nitride surface. Post-polish cleaning uses dilute oxalic acid at pH 3 for 30 s to remove copper-benzotriazole complex, followed by a DI water rinse; extended exposure to oxalic acid above 60 s attacks the copper sidewalls at the redistribution line edges. Particle adders above 0.12 µm are controlled below 60 per wafer, and trench defect inspection on a patterned packaging wafer is performed with a scanning electron microscope or automated optical inspection. The terminal surface must show no copper corrosion staining, no nitride cracks at the die edge, and no slurry residue in the 5 µm to 20 µm wide redistribution lines. This application is a deep-dive zone because small deviations in pH, inhibitor concentration, or pad temperature cause simultaneous copper corrosion and nitride rate collapse.

Power module substrates fabricated from gas-pressure-sintered silicon nitride with average grain size 1.0 µm to 2.0 µm and thermal conductivity 80 W/m·K to 100 W/m·K are polished with an electronic-grade slurry before active metal brazing of copper foil. The as-sintered surface typically shows a nitrogen-rich skin, grain pull-out pits, and waviness that must be reduced to meet partial discharge and thermal cycling reliability requirements. In this application the slurry is a high-purity colloidal silica dispersion with D50 particle size 20 nm to 40 nm, diluted 1:2 to 1:5 with deionized water, and operated at pH 9.0 to 10.0. Polishing is performed on a single-sided ceramic polisher with a nonwoven fabric pad; downforce ranges from 3.0 psi to 6.0 psi, platen speed from 40 rpm to 70 rpm, and slurry flow from 100 mL/min to 200 mL/min. Material removal rate for the final CMP stage is intentionally low, 30 nm/min to 80 nm/min, because a preceding diamond lapping stage establishes flatness and the final step removes subsurface damage rather than bulk material. Post-polish surface roughness measured by laser confocal microscopy over 0.5 mm × 0.5 mm is held below 0.05 µm Ra, and global thickness variation across a 190 mm × 138 mm panel is kept below 5 µm. Metallic contamination from the slurry must be minimized because residual iron, copper, or nickel on silicon nitride substrates creates conductive paths that degrade partial discharge performance under 650 V class IGBT and 1200 V class SiC MOSFET operation. Acceptance limits for surface metal contamination after cleaning are typically below 100 ppb per element by vapor-phase decomposition inductively coupled plasma mass spectrometry, with sodium and potassium below 50 ppb. The standard grain size is confirmed by linear intercept per ASTM E112-13, and the polishing bay is maintained to ISO 14644-1:2015 Class 5 to prevent particle contamination during drying. A key process conflict is that excessive downforce above 6 psi or use of low-purity slurry creates microcracks that propagate along grain boundaries; these cracks cannot be healed by final CMP and are detected by dye penetrant inspection or scanning acoustic microscopy after copper bonding. The polished substrate proceeds to active metal brazing, where copper foil is bonded under 800 °C to 850 °C in a vacuum furnace; surface roughness outside the 0.05 µm Ra limit causes void formation at the copper-silicon nitride interface and reduces thermal cycling endurance below the required 500 cycles from −40 °C to 150 °C.

MEMS Diaphragm Thinning: Slurry Dilution, Residual Stress, and Post-CMP Clean Limitations

Free-standing or partially released LPCVD silicon nitride membranes used in acoustic microphones and pressure sensors require final thickness control in the 50 nm to 200 nm range, with residual stress maintained below 250 MPa tensile to avoid buckling. Polishing is performed before release on the front side of the wafer using an electronic-grade slurry with reduced abrasive solid content, usually 1 wt% to 3 wt%, D50 particle size near 20 nm, and pH 8.0 to 9.0. The slurry is diluted 1:8 to 1:12 with ultrapure water to achieve a low removal rate of 10 nm/min to 40 nm/min, which allows thickness endpointing by spectroscopic ellipsometry or reflectometry across the diaphragm array. Polishing downforce is limited to 0.5 psi to 1.0 psi, platen speed is 30 rpm to 50 rpm, and slurry flow is 100 mL/min to 150 mL/min. A hard pad with Shore D hardness above 52 is used to avoid pad compliance-induced edge rounding at the membrane perimeter, but the high hardness increases microscratch risk, so the slurry is filtered through 0.05 µm point-of-use filtration. Surface roughness after polishing must be below 0.2 nm RMS over 1 µm × 1 µm atomic force microscopy scans to preserve acoustic signal-to-noise ratio. Post-CMP cleaning uses single-wafer dilute ammonium hydroxide at pH 9 with low-power megasonic energy below 20 W to avoid rupturing partially released membranes; batch immersion cleaning is prohibited for wafers with diaphragms thinner than 100 nm because capillary forces cause stiction and fracture. The slurry’s pH drift is constrained to 0.1 pH units per day because the low abrasive loading has reduced buffering capacity. Published data for the specific normal-stress evolution during CMP of 50 nm membranes is limited, so film thickness and wafer bow are monitored at 9 points across the wafer before and after polishing. A production lot is rejected if within-wafer diaphragm thickness nonuniformity exceeds 3 nm at 1σ or if post-polish adders above 0.06 µm exceed 20 per wafer. The terminal device is a condenser microphone diaphragm or piezoresistive pressure-sensor membrane with high dimensional consistency and low surface damage.