In semiconductor front-end wafer fabrication, wet removal of silicon nitride is performed with electronic/EL grade etchant maintained at 85 wt% H₃PO₄, a composition near the boiling point of 158 °C. The acid is specified under SEMI C35 with mobile cations below 10 ppb and should be used with ASTM D5127 Type E-1 rinse water. The primary film attacked is low-pressure chemical vapour deposition Si₃N₄ serving as pad mask, stress liner, or contact etch stop layer. Bath preparation includes a dilute hydrofluoric acid pre-dip at 0.5 wt% for 15–30 s to remove native oxide; without this step, initiation delays of 30–120 s and non-uniform etch fronts across a 25-wafer PFA cassette are observed. The etch bath is held at 160 ± 2 °C in a quartz immersion tank equipped with a reflux condenser, near-infrared water sensor, and conductivity-based concentration monitor. DI water spiking at 0.1–0.2 L/h per 100 L acid volume compensates for evaporative water loss and preserves the selectivity window. Stoichiometric LPCVD Si₃N₄ etches at 4–6 nm/min, while thermal SiO₂ loss remains 0.2–0.5 nm/min, yielding selectivity near 20:1 to 30:1. Process times of 20–45 min are typical for nitride thicknesses from 100 nm to 200 nm. The terminal wafers enter gate oxidation, spacer deposition, or silicide formation in logic, DRAM, and 3D NAND flows. Operational boundaries include a bath temperature ceiling of 168 °C, above which dissolved silica precipitates as silicate particles and oxide loss accelerates. Bath bleed-and-feed at 10–15 vol% per production batch controls dissolved silica below 80–120 ppm and maintains particulate counts below 100 counts/mL at 0.2 µm. Cleanroom environment control follows ISO 14644-1 Class 3.

What Process Window Protects Thermal Oxide During STI Hard Mask Removal?

Shallow trench isolation hard mask removal after CMP presents the most demanding wet etch selectivity path. The silicon nitride hard mask is 150–250 nm thick over high-density plasma oxide fill. The etchant formulation remains 85 wt% H₃PO₄, but controls are tighter than diffusion mask removal. Temperature must be maintained at 160 ± 1 °C in a quartz bath with PID heaters and immersed quartz thermowells. At 165 °C, thermal oxide loss increases to 0.7–1.0 nm/min, and the selectivity to oxide drops below 10:1. At 170 °C the bath dehydrates toward pyrophosphoric acid; nitride etch rate falls while oxide attack accelerates. A wet nitrogen sparge of 0.3–0.5 L/min across the bath surface is commonly used to maintain water activity. Endpoint is determined by ellipsometry or reflectometry on monitor wafers after a timed etch. Overetch allowance is limited to 10–15% of the main etch to protect the underlying oxide step height. Failed bath control produces oxide loss in the active region corners, leading to junction leakage or narrow channel effect after transistor formation. Terminal parts are logic and memory wafers before gate oxidation. The wet bench uses PFA cassettes, quartz tanks, and 0.2 µm PTFE recirculation filters. Process air quality is held to ISO 14644-1 Class 3, and all wetted components are qualified for SEMI C35-grade acid service.

Compound semiconductor wafer processing for gallium-nitride RF and power devices applies silicon nitride etchant at lower thermal stress than CMOS front-end flows. PECVD SiN passivation on AlGaN/GaN high-electron-mobility transistor structures is opened before gate metal definition or after ohmic contact annealing. The bath is operated at 150–155 °C, not 160–165 °C, to limit metal stack diffusion at the Ni/Au gate interface and to reduce hydrogen-induced surface damage on the AlGaN barrier. The acid concentration is often reduced to 80–82 wt% for compound semiconductor applications, increasing water content and lowering oxide attack on any exposed AlOx or SiOx dielectric. Published etch rate data for this specific configuration is limited; GaN and AlGaN themselves can undergo slight surface roughening in boiling phosphoric acid, so bath qualification must include epitaxial monitor coupons and photoluminescence before lot release. Typical immersion times are 5–15 min for nitride thicknesses of 50–150 nm. The end product is a passivated high-frequency transistor or power diode wafer with field-plate dielectric openings aligned to source and drain contacts. The etchant must meet SEMI C35 trace metal limits and additional chloride-free and low-sulphur packaging requirements to prevent pad corrosion. Rinse water is monitored to ASTM D5127 Type E-1 specifications.

MEMS Nitride Mask Removal After Alkaline Silicon Release

In microelectromechanical systems manufacturing, low-stress LPCVD silicon nitride acts as a hard mask during potassium hydroxide or tetramethylammonium hydroxide bulk micromachining and as a structural membrane in pressure sensors and microbolometers. After deep silicon cavity release, the nitride mask often must be stripped selectively from underlying silicon dioxide, doped silicon, or thin metal bond pads. The wet etch bath uses 85 wt% electronic-grade H₃PO₄ at 155–160 °C in a quartz tank. The primary process conflict is that alkaline release residues can neutralize the acid surface locally, creating non-uniform initiation. A pre-clean in 0.1–0.5 wt% hydrochloric acid or dilute buffered HF removes potassium and sodium residues before immersion. LPCVD nitride removal in this bath proceeds at 3–5 nm/min; low-stress nitride with silicon-rich composition may etch 20–30% slower than stoichiometric LPCVD films. Silicon dioxide loss is held below 0.3 nm/min by limiting temperature to 160 °C and monitoring water content. A production-scale wet bench for MEMS uses 0.2 µm PTFE filters and quartz carriers to prevent particle adhesion to released membranes. Terminal devices include piezoresistive pressure sensors, acceleration switches, acoustic transducers, and uncooled infrared microbolometers. The electronic-grade specification is critical for CMOS-integrated MEMS where mobile cation contamination above 1×10¹⁰ atoms/cm² shifts threshold voltages in adjacent readout circuitry. Cleanroom handling follows ISO 14644-1 Class 4 for MEMS where sacrificial release residues are more difficult to control.

When Silicon Nitride Passivation Must Be Removed Before Under-Bump Metallization in Wafer-Level Packaging

Wafer-level chip scale packaging and copper pillar bumping flows incorporate silicon nitride passivation over aluminium bond pads or copper redistribution lines that must be removed selectively to create a clean metal surface for under-bump metallurgy. Dry etch is the default patterning route because photoresist cannot survive the hot acid bath, but wet nitride removal is used for blanket rework, edge-bead removal, or full-wafer passivation strip before metal deposition. The etchant is maintained at 160–165 °C; PECVD silicon nitride with high hydrogen content etches at 8–15 nm/min, requiring immersion times of 15–45 min for passivation layers from 200 nm to 600 nm. Hot phosphoric acid attacks exposed aluminium at this temperature; therefore the process is limited to wafers where aluminium pads are not yet defined or where a sacrificial oxide layer protects the aluminium. The bath must use type PFA fittings and quartz piping; metallic wetted parts, especially stainless steel, leach iron and chromium into the acid and breach SEMI C35 cation limits. Post-etch rinsing with deionized water at 45–60 °C prevents acid gel formation on the wafer surface. Terminal packages include fan-in and fan-out WLP devices, memory multi-chip packages, and RF front-end modules. Package qualification includes mobile ion contamination testing to confirm that no residual phosphorus or silicate contamination remains at the metal interface before under-bump metallization.

While plasma etch remains the dominant patterning route in flat-panel display fabrication, wet silicon nitride etchant is deployed for panel rework and full-film strip where high-temperature acid exposure can be isolated from photoresist. PECVD silicon nitride serves as the principal gate dielectric, passivation, and interlayer dielectric in amorphous silicon and low-temperature polysilicon thin-film transistor arrays. In rework tanks, electronic-grade etchant at 80–85 wt% removes PECVD nitride from 1500 × 1850 mm glass substrates after photoresist stripping. Immersion or spray exposure lasts 10–30 min, and panel tilt in spray tools is adjusted to prevent acid pooling on device corners. The formulation must contain sub-10 ppb sodium and potassium; mobile cation transfer to the TFT channel is known to shift threshold voltage by 0.1–0.5 V at contamination levels above 1×10¹¹ atoms/cm². Process tanks use quartz or PVDF construction, and filtration at 0.2 µm maintains particle cleanliness. Exposed aluminium gate lines are attacked at the operating temperature; rework is therefore performed before gate metal deposition or after full passivation where aluminium is fully covered by an inert overlayer. Terminal products are display panels for mobile, automotive, and television backplanes after rework and reprocessing. Rinse water and cleanroom protocols are controlled to ASTM D5127 and ISO 14644-1 Class 5 limits for panel processing.