Across 300 mm reclaimed-wafer lines, the nitric acid–hydrofluoric acid–acetic acid mixture classified as silicon etchant Electronic/EL grade is applied to remove damaged lattice layers from stripped, rejected, or reclaimed test wafers before repolishing. The bath make-up ratio is typically 5:1:2 to 7:1:2 by volume, using 69.0–70.0 wt% HNO₃, 49.0–49.5 wt% HF, and 99.8 wt% glacial acetic acid. This composition shifts the rate-limiting step from silanol dissolution to nitrosyl intermediate transport when the HNO₃ volume fraction exceeds 70%. The oxidation–dissolution couple can be summarised as Si + 4HNO₃ → SiO₂ + 4NO₂ + 2H₂O and SiO₂ + 6HF → H₂SiF₆ + 2H₂O; acetic acid moderates the dielectric constant of the bath and thickens the diffusion boundary layer. Batch-to-batch etch-rate variance of 0.2–0.4 µm/min arises from nitrous acid off-gassing at 21 ± 0.5 °C, requiring metered HNO₃ replenishment and continuous bath-density monitoring. The production process uses 50-wafer PFA immersion carriers, a 0.2 µm fluoropolymer recirculation filter, and a wet bench constructed without borosilicate glass because free HF attacks silicate networks; all wetted surfaces are PFA, PTFE, or PVDF. Rinsing follows with ultrapure water at ≥18.2 MΩ·cm at 25 °C per ASTM D5127-13, then drying in an isopropyl alcohol vapour dryer. Compliance is anchored to SEMI C13-0302 Grade 2 for nitric acid and SEMI C14-0302 Grade 2 for hydrofluoric acid, verifying Fe ≤10 ppb, Ni ≤5 ppb, Cu ≤5 ppb, Na ≤10 ppb, and particle counts ≤25 counts/mL at ≥0.5 µm. Reclaimed output moves into lithography qualification wafers, CMP dummy wafers, thermal process monitor wafers, and oxidation dummy wafers. A documented limitation is that acetate ester by-products accumulate after prolonged bath life; once free acetic acid drops below 95% of initial charge, etch uniformity degrades and the bath must be drained and restabilised before recommissioning.

Because the same acid mixture is not universally interchangeable across downstream sectors, the following production-bath compliance matrix is applied to blended HNA electronic/EL-grade systems. The limits reflect component acid specifications rather than generic acid-water dilution, and they must be re-verified after blending because impurity partitioning changes with the acid proportion and bath age.

How Does the HNO₃:HF Ratio Shift Surface Reflectance in Diamond-Wire-Sawn Multi-Si?

For diamond-wire-sawn multicrystalline wafers entering acid texturing, the production bath is a cold 6–10 °C HNA mixture with a volumetric ratio of 1:2.5:1.5 to 1:4:2 for 49% HF, 69% HNO₃, and deionised water, with a common centre point at 1:3:2. The process is isotropic and creates a microporous surface that suppresses specular reflection; the ratio is manipulated because a high HNO₃ fraction increases oxide initiation, whereas a high HF fraction accelerates oxide dissolution. At the 1:3:2 centre point, silicon removal is typically 3–5 µm per side, with surface reflectance in the 400–700 nm range dropping below 20% on non-passivated wafers; current gain is subsequently modified by rear passivation and SiNₓ:H deposition. The production line is an inline horizontal wet bench equipped with PTFE wafer rollers, dual acid feed lines, and a fluoropolymer heat exchanger; bath temperature excursions above 14 °C trigger uncontrolled nitrous gas evolution, orange staining, and non-uniform etch craters at saw-damage intersections. Compliance for acid components follows SEMI C13-0302 and SEMI C14-0302 Grade 2, while the etch room operates under ISO 14644-1:2015 Class 7 with point-of-use exhaust for HF vapour. The output cells feed into multicrystalline silicon solar module lines with wafer formats from 156.75 mm pseudo-square to 166 mm semi-square, yielding modules qualified under IEC 61215-1:2016 after cell interconnection and lamination. The primary process constraint is that diamond-wire saw damage cannot be fully homogenised by acid texturing alone; wafers with sub-surface cracks deeper than 8 µm typically require a prior mechanical etch-back, a proprietary additive package, or reduced etch-depth targeting to avoid cell cracking at metallisation.

In released MEMS gyroscope structures, the attack on exposed silicon proceeds through a diffusion-controlled oxidation–dissolution couple in which nitric acid passivates the silicon surface, HF strips the resulting oxide, and acetic acid suppresses nitric acid dissociation to control free nitrous acid concentration. Production etchant is blended at a volumetric ratio of 2:1:1 to 1:1:1 HNO₃ (69.5%):HF (49%):CH₃COOH (99.8%) and operated at 10–12 °C to keep etch rate at 0.8–1.2 µm/min on lightly doped p-type (100) silicon. The downstream process begins after deep reactive-ion etching defines comb fingers or proof-mass trenches; wafers are transferred into a PFA etch tank with nitrogen bubble agitation and etched until the target undercut reaches 0.5–2.0 µm, depending on the required mechanical spring constant. The buried oxide in SOI is not a perfect etch stop: HF in the mixture attacks thermal oxide at roughly 1–3 nm/min, so endpoint is governed by real-time visual or interferometric reflectance rather than infinite selectivity. After etching, deionised water rinsing at ≥18.2 MΩ·cm is followed by isopropanol displacement and supercritical CO₂ drying to avoid release stiction. Chemical conformance is verified against SEMI C13-0302 and SEMI C14-0302 Grade 2, with additional transition-metal limits of Cu ≤5 ppb, Fe ≤10 ppb, and Na ≤10 ppb to protect gate oxide integrity. The output devices include automotive airbag accelerometers, electronic stability control yaw-rate sensors, MEMS microphones, and RF MEMS switches. The principal failure mode is pattern-density-dependent undercut variation: high-aspect-ratio springs located near large open cavities etch faster than isolated fine features, requiring feature-size compensation in mask tape-out and periodic etch-rate verification on short-loop dummy wafers.

When Through-Silicon Via Reveal Moves from Plasma Etch to Single-Wafer Spin Processing

At the point where backgrinding stops near a buried via tip, an HNA wet etch removes the remaining 3–6 µm of silicon on a 300 mm wafer to expose electroplated copper through-silicon vias for subsequent redistribution-layer metallisation. The spin processor dispenses a backside formulation of HF(49%):HNO₃(70%):DI water = 4:1:1 to 5:1:1 by volume at 17–20 °C; the higher HF content etches silicon while limiting copper dissolution compared with chemistries containing more than 25 vol% HNO₃. Platen speed is held at 600–900 rpm, chemical flow at 1.0–1.5 L/min, and silicon removal is monitored by per-wafer metrology rather than fixed-time processing because incoming total-thickness variation from backgrind varies from 2 µm to 8 µm across a cassette. A process conflict exists between uniform radial removal and over-etch into exposed copper: at temperatures above 22 °C, copper oxidation increases even with the high HF ratio, generating bath contamination and via-surface roughening. Bath compliance requires SEMI C13-0302 and SEMI C14-0302 Grade 2 acid components, with Cu concentration in the etch bath maintained below 10 ppb by point-of-use purification; wafer cassettes and dispense lines are PFA or PTFE. The output enters temporary or permanent bonding flows, yielding 2.5D interposers, high-bandwidth memory stacks, and fan-out wafer-level packaging. A documented operational boundary is that backside delamination may occur if the spin process follows backgrind without a stress-relief step or if the dicing tape temperature exceeds 40 °C during chemical dispense; this condition necessitates platen cooling on some single-wafer tools.

Rather than processing whole wafer batches, silicon etchant in failure-analysis workflows is deployed in microliter aliquots to strip the silicon substrate after die-level deprocessing. A common localised formulation is 3:1:1 by volume HNO₃(69%):HF(49%):CH₃COOH, applied in 20–100 µL increments at an ambient temperature of 23 ± 2 °C under a stereozoom microscope. The process begins with mechanical thinning to 100–200 µm die thickness, followed by short CF₄ plasma removal of passivation, then microdrop etching; endpoint is judged by colour shift from silver to grey to visible diffusion regions. Equipment consists of a platinum/PFA micropipette or syringeless dispense system, an anti-static work surface meeting ANSI/ESD S20.20-2021, and fume extraction sufficient to maintain HF vapours below the site action level. Because the procedure is destructive and often required for patent litigation or process-excursion diagnosis, laboratory methods conform to ISO/IEC 17025:2017, with batch records traceable to individual die coordinates, lot numbers, and dispense volumes. Acid grade is maintained at SEMI C13-0302 and SEMI C14-0302 Grade 2 to avoid introducing trace-metal artefacts into failure signatures. The terminal outputs are SEM cross-sections, transmission electron microscopy lamellae, backside infrared emission microscopy on thinned dies, and formal failure-analysis reports. The process is unsuitable for quantitative yield reclaim and cannot remove copper bond wires or lead-free solder bumps unless those materials are stripped before silicon etching.

Silicon Interposer Cavity Etching: Mask Design and Bath Composition Constraints

Cavity silicon etching for wafer-level hermetic lids uses a low-HF HNA ratio to produce rounded, isotropic cavities with depth-to-mask undercut ratios of approximately 1:1. The bath is prepared at 6:1:3 by volume HNO₃(70%):HF(49%):CH₃COOH and held at 25 ± 1 °C; the resulting etch rate on (100) silicon is 2–4 µm/min, with cavity depths controlled between 30 µm and 100 µm by timed immersion. A 200–300 nm low-pressure chemical vapour deposition silicon nitride hard mask is patterned by double-sided lithography; mask undercut at the etch endpoint equals the cavity depth, so the mask opening is drawn smaller than the intended cavity floor by the target depth. The process uses a PFA/PTFE immersion bath with magnetic or pneumatic agitation, followed by hot phosphoric acid removal of the nitride mask. Chemical purity follows SEMI C13-0302 and SEMI C14-0302 Grade 2; because silicon nitride mask lifting is a known failure mode, the bath’s HF activity must not exceed the 6:1:3 centre point by more than 5%. Output devices include wafer-level capping structures for microbolometers, hermetic MEMS resonators, radio-frequency packages, and silicon optical bench cavities. Published industrial data for this specific low-HF cavity formulation is limited compared with established PV and MEMS texturing chemistries; most qualified volume lines use internal design-of-experiment tables generated on their specific mask stack and cavity geometry, rather than relying on public universal etch-rate curves.