| HS Code | 408437 |
| Productname | Silicon Etchant |
| Chemicalcomposition | Hydrofluoric acid, Nitric acid, Acetic acid (HNA) |
| Appearance | Clear colorless liquid |
| Odor | Sharp, pungent, irritating odor |
| Density | 1.13 g/cm3 at 20°C |
| Ph | <1 |
| Boilingpoint | Approximately 120°C |
| Meltingpoint | Approximately -7°C |
| Solubility | Miscible with water in all proportions |
| Etchrate | 1 to 5 micrometers per minute at 20°C |
| Selectivity | Etches silicon preferentially over silicon dioxide and silicon nitride |
| Vaporpressure | Approximately 20 mmHg at 20°C |
| Storagetemperature | 15 to 25°C in tightly sealed container |
| Shelflife | 6 to 12 months if stored properly |
As an accredited Silicon Etchant factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.
| Packing | Silicon etchant packaged in 1L HDPE bottle with child-resistant closure, corrosive warning labels, and tamper-evident seal. |
| Container Loading (20′ FCL) | Loading Silicon Etchant in 20′ FCL: secure certified drums upright, segregate, label hazardous, brace firmly, ventilate. |
| Shipping | Silicon etchant ships as a corrosive/hazardous chemical. It requires UN-rated containers, leak-proof sealing, and proper labeling. Transport follows strict IATA/IMDG/DOT regulations, with temperature controls if needed. Ground or air freight is available only through certified hazmat carriers, ensuring safe handling and compliance. |
| Storage | Store silicon etchant in a cool, dry, well-ventilated area inside clearly labeled, tightly sealed containers made of acid-resistant materials such as polyethylene or PTFE. Keep it away from incompatible substances, particularly bases, metals, and glass, and use secondary containment to manage spills. Follow all safety and regulatory guidelines. |
| Shelf Life | Shelf life is typically 6 months when stored properly in sealed original containers, away from light, heat, and moisture. |
On a 300 mm backgrinding line, subsurface silicon damage extends beyond the visible grind mark depth after rough and fine grind wheels are used to thin wafers for stacked-die packages. Mechanical abrasion generates microcracks and tensile stress at the backside that can reduce die fracture strength during dicing and die attach. Acidic silicon etchant composed of nitric acid, hydrofluoric acid, and acetic acid removes this damaged layer isotropically. The removal depth is governed by the total thickness reduction budget. Stress relief etches after fine grinding commonly target 5–20 µm of silicon removal, depending on final die thickness and diamond wheel grit sequence. In a PFA immersion wet bench with recirculation pumps and a heat exchanger, the bath temperature is held within ±1 °C to prevent etch-rate drift. A HNA bath with oxidant-to-etchant ratios adjusted for 0.5–20 µm/min removal produces a smooth backside surface. Bath ageing shifts the etch rate as HNO3 and HF are consumed and hexafluorosilicic acid accumulates. Continuous filtration at 0.2 µm removes particulates. Gas extraction prevents nitrogen oxide buildup above the freeboard. Front-side protection tape must withstand the acidic mixture without lifting; adhesion loss exposes active circuitry to silicon removal and metal attack. Spectroscopic reflectometry verifies final silicon thickness and total thickness variation after rinse and spin dry. Trace metal limits for the etchant are aligned with SEMI C1 chemical quality guidance. Cleanroom operation at the wet bench follows ISO 14644-1 Class 5 particulate limits.
Temperature nonuniformity across a 25-wafer KOH batch immediately changes the thickness of suspended diaphragms in silicon pressure sensors. At 80 °C, a 30 wt% KOH solution etches the Si(100) plane at 1.0–1.4 µm/min, while the Si(111) plane etches more than 100 times slower. This anisotropy enables bulk micromachining of cavities, membranes, and inertial masses through openings defined in hard masks. TMAH at 25 wt% and 80 °C etches Si(100) at 0.4–0.8 µm/min and is alkali-metal-free. That property makes TMAH applicable to CMOS-integrated MEMS where potassium contamination is unacceptable. Potassium ions diffuse rapidly in thermal oxide and shift transistor threshold voltage. KOH is therefore restricted to non-CMOS or pre-CMOS process stages. Etch-rate stability depends on water loss from the heated bath, dissolved silicon concentration, and the presence of boron or phosphorus doping profiles. A p+ boron etch stop above 1×1019 cm-3 can reduce the etch rate by more than 50 times, enabling precise membrane formation when timed etch control is insufficient. Hydration of etched surfaces and hydrogen bubble release are managed with megasonic agitation or wafer movement. Without agitation, bubble masks leave pyramidal protrusions on resonator surfaces. Batches are processed in quartz or PFA tanks with temperature control within ±0.5 °C and independent dosing pumps for hydroxide and deionized water. Bath lifetime is limited by carbonate uptake from air and silicate accumulation. Replenishment without total dump is acceptable only if silicate concentration and etch-rate coupons satisfy the process control plan.
| Parameter | KOH 30 wt% | TMAH 25 wt% |
|---|---|---|
| Si(100) etch rate | 1.0–1.4 µm/min | 0.4–0.8 µm/min |
| Etch selectivity to thermal SiO2 | ≈100:1 | >1000:1 |
| Alkali metal contamination | Potassium present | None |
| CMOS compatibility | Limited to pre-CMOS or non-CMOS | Suitable for CMOS-integrated MEMS |
| Primary process limitation | Mobile ion contamination | Higher cost, lower etch rate |
Inline alkaline texturing of monocrystalline photovoltaic wafers produces randomly oriented pyramids that reduce front-surface reflectance after antireflective coating deposition. Potassium hydroxide or sodium hydroxide at 1–5 wt% is heated to 78–85 °C and dosed with isopropanol or sodium silicate to control pyramid nucleation density. Pyramid size typically falls between 2–8 µm. Weighted reflectance after texturing without silicon nitride antireflective coating is typically 10–13%. Hydrogen gas generated during alkaline etching must be removed by bath recirculation and wafer walking. Stagnant bubble films produce streaky low-pyramid zones and nonuniform sheet resistance. Multicrystalline wafers cannot be texturized effectively by anisotropic alkaline etching because grain orientation varies across the wafer. Acidic silicon etchants based on HF/HNO3/H2O at 5–12 °C create isotropic porous silicon and remove saw damage. Silicon removal per side in acid texturing is usually 3–8 µm, compared with 5–15 µm for monocrystalline alkaline texturing. Bath life depends on silicon loading, additive degradation, and nitrate reduction byproducts. Gravimetric silicon determination or UV-Vis bath analysis is used to control replenishment. The acid texturing reaction generates nitrogen oxides; enclosed wet scrubbers and acid-resistant deck materials are required on production lines.
| Parameter | Monocrystalline alkaline | Multicrystalline acid |
|---|---|---|
| Chemistry | KOH/NaOH + additive | HF/HNO3/H2O |
| Temperature | 78–85 °C | 5–12 °C |
| Silicon removal per side | 5–15 µm | 3–8 µm |
| Texture morphology | Random pyramids | Porous isotropic surface |
| Weighted reflectance after texturing | 10–13% | 20–25% |
| Critical control variable | Additive concentration and pyramid size | Bath temperature and silicon loading |
Wet silicon etch for polysilicon gate and sacrificial layer removal is not a single-chemistry operation. HNO3 oxidizes silicon to silicon dioxide, and HF dissolves the oxide. Acetic acid dilutes the system and shifts the oxidation-etch balance. A high-HNO3 formulation etches at a rate limited by HF transport, producing an isotropic profile with severe undercut when polysilicon is exposed through a resist or oxide mask. A high-HF formulation etches more slowly and is limited by HNO3 availability at the silicon surface. For polysilicon gates, selectivity to thermal oxide is controlled by the acetic acid ratio and bath temperature. On a production wet bench, a recirculating HNA bath in a single-wafer spray processor is preferred for polysilicon removal because it reduces etch-product accumulation and provides better endpoint control than an immersion bath. Endpoint is detected by laser reflectance or open-circuit potential change. Overetch is limited to 10–20% of the target removal to minimize gate oxide loss. Spectroscopic ellipsometry is used after etch to verify gate oxide thickness because etch selectivity to silicon dioxide is not constant over bath age. Nitrogen oxides generated by HNO3 reduction require enclosed exhaust and wet scrubbing. Batch-to-batch variance in HNO3 concentration from ambient evaporation changes the etch rate. Density and free-acid titrations are therefore performed before each lot. This chemistry is not used for advanced high-k/metal-gate front-end patterning where Cl2/HBr plasma etch dominates, but it remains relevant for polysilicon sacrificial layers, power device field plates, and analog CMOS low-volume foundry flows. A final rinse in ultrapure water with dissolved oxygen below 10 ppb is required to prevent pitting of exposed silicon surfaces.
Mask openings used for through-wafer channels expand laterally at roughly the same rate as vertical etch if agitation is insufficient. In a silicon-on-glass microfluidic device, an HNA etch through a silicon nitride hard mask produces rounded channel cross-sections. A 50 µm-deep channel etched from both sides of a 200 µm wafer will expand each opening laterally by approximately 50 µm. The final top width equals the mask opening plus 100 µm when etch is perfectly isotropic. Actual expansion is lower at the channel bottom because etch-product dilution and hydrogen bubble accumulation reduce the local etch rate. Published data for this specific configuration is limited, particularly for surface roughness after prolonged HNA exposure of pre-bonded borosilicate glass. Wet isotropic etching remains relevant when deep reactive ion etching is unavailable or when low capital cost is required for prototype runs. The hard mask must be pinhole-free. Undercut is monitored with optical microscope measurements at the mask edge. Failure to remove residual fluorinated deposits after etching degrades glass-silicon anodic bonding yield.
For a wafer reclaim pool of 300 mm test wafers, silicon removal depth is not a fixed value across the pool. Thermal oxide, TEOS, polysilicon, silicon nitride, and implanted silicon are stripped in separate chemical steps before bulk silicon etching. The silicon etchant removes residual silicon defects and controlled thickness from the wafer surface after film removal. A reclaim line may target 10–30 µm of bulk silicon removal per cycle to eliminate residual contamination and surface damage before repolishing. The exact removal depth is determined by the number of previous reclaim cycles, bow/warp, and the minimum allowable wafer thickness in the target fab. Alkaline silicon etchants may be used where roughness control is more important than isotropic behavior. Acid HNA baths are used for high-throughput reclaim with etch rates above 5 µm/min. Process control includes total thickness variation after etch, surface particle count, and trace metal analysis against SEMI C1 limits. Wafer reclaim reduces environmental burden compared with new wafering, but repeated silicon etching creates edge chipping and increases warp. After 5–10 cycles, the wafer is typically downgraded to dummy grade or scrapped. The etchant bath in reclaim contains high silicon loads and must be filtered and replenished at shorter intervals than in thinner-stack front-end wet benches. Disposal of hexafluorosilicic acid and nitrate byproducts requires fluoride precipitation and nitrate removal in waste treatment. Without control of these waste streams, reclaim costs exceed cost savings.
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Silicon Etchant is supplied as an aqueous potassium hydroxide concentrate with a certified KOH content of 45.0 ± 0.5 wt%. The product is filtered through a 0.1 µm PTFE cartridge and released by lot-specific analysis against the water quality requirements of ASTM D5127 Type E-1.2. The concentrate is intended for anisotropic bulk micromachining of (100) monocrystalline silicon wafers in microelectromechanical systems, pressure sensor, microfluidic, and inkjet nozzle fabrication. As-supplied impurity ceilings are ≤ 20 ppb sodium and ≤ 5 ppb each for Fe, Cu, Ni, Cr, and Zn by inductively coupled plasma mass spectrometry. The specific gravity at 25 °C is 1.45–1.48 g/cm³. The material is packaged in fluoropolymer-lined containers and diluted on site with ultrapure water to a working concentration between 20 wt% and 30 wt% KOH depending on the required etch rate and selectivity. Model designation is assigned by the manufacturing site from the registered concentration grade and impurity class; equivalence between lots is established by KOH assay, trace-metal lot release data, and bath etch-rate qualification rather than by trade name alone.
| Lot-release parameter | Typical value | Analytical method |
|---|---|---|
| KOH concentration | 45.0 ± 0.5 wt% | Acid-base titration |
| Specific gravity at 25 °C | 1.45–1.48 g/cm³ | Oscillating U-tube densitometer |
| Sodium | ≤ 20 ppb | ICP-MS, direct aspiration |
| Fe, Cu, Ni, Cr, Zn | ≤ 5 ppb each | ICP-MS, direct aspiration |
| Chloride | ≤ 5 ppm | Ion chromatography |
| Particles ≥ 0.5 µm | ≤ 100 counts/mL | Optical particle counter |
After dilution to 30 wt% KOH and heating to 80 °C, the etchant removes Si(100) at a reported range of 0.8–1.6 µm/min in a recirculating polypropylene bath with megasonic agitation. The {111} planes etch at a rate that is two to three orders of magnitude lower; published anisotropy ratios for 30 wt% KOH at 80 °C commonly fall between 50:1 and 400:1, depending on wafer dopant concentration, dissolved silicon, and local hydroxide transport. The vertical etch rate is not an intrinsic constant but a process variable governed by temperature, bath age, and pattern geometry. Temperature dependence follows an Arrhenius relationship with apparent activation energy of 0.55–0.65 eV across the 60–90 °C interval; therefore, a bath temperature change of 10 °C changes the Si(100) rate by approximately a factor of two. A control tolerance of ± 1 °C is maintained in production because infrared pyrometer measurements on wafer surfaces exposed to ambient air can read 2–3 °C below the bulk liquid temperature inside the cassette. Heater power density is limited to 1.5 W/cm² on PTFE-coated elements to prevent local boiling at the heater surface; recirculation at 10–20 L/min per 100 L bath volume maintains the thermal gradient below ± 0.5 °C across the cassette.
The etch rate declines as dissolved silicon accumulates. At dissolved silicon concentrations above 10 g/L, the Si(100) rate typically decreases by 15–30% relative to fresh bath. Above 20 g/L, silicate precipitation produces micromasking defects observed as surface haze under collimated light. For a 150 mm wafer with 50 µm targeted silicon removal, the mass dissolved per wafer is approximately 2.06 g, based on a silicon density of 2.33 g/cm³ and full front-surface exposure. A 40 L bath can therefore process roughly 290 wafers before dissolved silicon approaches 15 g/L. Deeper cavity etches, such as 500 µm through-wafer removal, reduce the equivalent lot size to approximately 29 wafers. Published production-line data for this specific impurity class are limited; the etch-rate ranges quoted are drawn from bulk micromachining studies with comparable KOH concentrations and bath ageing conditions.
The working bath is contained in polypropylene or PVDF tanks because potassium hydroxide at 80 °C attacks borosilicate glass at a measurable rate. Wafers are held in PTFE or PFA cassettes and are pre-cleaned in 0.5–2% hydrofluoric acid for 30–60 s to remove native oxide before immersion. Hydrogen released by the silicon dissolution reaction accumulates as bubbles on horizontal surfaces; without active bubble management, pyramidal hillocks and local roughness increase. Megasonic agitation at 40–80 kHz and 0.5–2.0 W/cm² transducer power is applied to detach hydrogen before it coalesces. In addition, isopropyl alcohol may be added at 5–10 vol% to reduce surface tension; this addition lowers the vapor-phase flash point and requires the wet bench to be interlocked with flammable vapor detection and exhaust flow verification. Production recipes frequently use a 15° cassette tilt with periodic rotation every 30 s to avoid bubble trapping at the mask edge.
Bath replacement is triggered when the Si(100) open-field etch rate on a monitor wafer deviates by more than ± 10% from the qualified reference value. The monitor wafer is a p-type (100) silicon wafer with 1–10 Ω·cm resistivity masked with LPCVD silicon nitride; the etch depth is measured by stylus profilometry after 60 min of immersion. In addition, a dissolved silicon load approaching 20 g/L promotes precipitation of potassium silicates on heater surfaces and piping; signs of saturation include increased turbidity and a rise in pressure drop across the 0.45 µm recirculation filter. The bath is cooled to 40 °C before filter replacement to reduce thermal shock to fluoropolymer piping and to lower the risk of aerosol release.
Membrane fabrication on 200 mm wafers requires different bath management because the ratio of silicon mass to bath volume is higher. In a 100 L bath processing 200 mm wafers with 75% exposed silicon area, the dissolved silicon load rises by approximately 13.7 g per wafer for 250 µm removal. The 20 g/L threshold is reached after roughly 145 wafers, assuming minimal drag-out. As the bath ages, the {111} stop-plane integrity is affected less than the {100} rate, but the undercut rate at mask edges increases because reaction byproducts accumulate near the mask-silicon interface. Etch rate uniformities of ± 2% across a 200 mm wafer require wafer rotation and a recirculation diffuser plate positioned 15–25 mm below the cassette. Without the diffuser, impingement jets from the recirculation return line produce local rate maxima that exceed 4% relative to the wafer mean.
Potassium residues from this product are incompatible with front-end metal-oxide-semiconductor device processing because mobile potassium ions shift threshold voltages. Where the silicon etch occurs after aluminium deposition or in a CMOS line, the equivalent process uses 25 wt% tetramethylammonium hydroxide at 80 °C. The TMAH etchant removes Si(100) at 0.4–1.0 µm/min and retains crystal-plane anisotropy, but its rate is roughly 50–70% of KOH at comparable hydroxide concentration and temperature. TMAH does not eliminate aluminium attack. Reported aluminium etch rates for undoped TMAH range from 5 nm/min to greater than 30 nm/min at 80 °C depending on pH and silicon content; silicon-saturated TMAH formulations reduce the aluminium etch rate to below 10 nm/min by shifting the electrochemical potential.
For designs that require an isotropic profile rather than a crystallographic stop, a hydrofluoric–nitric–acetic acid mixture is used instead. Typical removal rates span 1–50 µm/min, with the rate depending on HF/HNO3 ratio, temperature, agitation, and wafer doping. Heavily doped p-type silicon etches faster under nitrate-rich conditions because of the higher density of holes at the surface. This isotropic chemistry does not provide {111} plane selectivity, and it attacks thermal silicon dioxide at a rate that is comparable to or higher than silicon in some formulations; oxide mask thickness must be at least 1.5 times the desired silicon removal depth when etch selectivity is uncertain.
Thermally grown silicon dioxide and low-pressure chemical vapour deposition silicon nitride are the primary hard masks used with the anisotropic etchant. At 80 °C in 30 wt% KOH, thermal SiO2 removal is generally reported below 2 nm/min; LPCVD Si3N4 removal is 0.05–0.2 nm/min depending on film stress and density. PECVD nitride with oxygen contamination etches faster and is not recommended when the required etch time exceeds 2 h. The minimum mask thickness is calculated as the worst-case mask etch rate multiplied by total silicon etch time, plus a residual allowance of 20% for pinhole coverage. For a 500 µm silicon cavity etched at 1.0 µm/min, the etch time is 500 min; a thermal oxide mask would lose roughly 1 µm if the oxide etch rate is 2 nm/min, which dictates a starting oxide thickness of at least 1.2–1.5 µm for hard-mask integrity.
The etchant cannot contact exposed aluminium, zinc, tin, or galvanically coupled metal films because alkaline attack releases hydrogen and damages metallization. Wafers with aluminium bond pads must be routed to TMAH-compatible processing or protected with an etch-stop layer qualified by a witness wafer exposed for the full anticipated etch time. When a device requires both front-side patterned metal and through-silicon etching, the sequence is organized so that potassium-bearing chemistry is completed before metal deposition, and the wafers receive an extended ultrapure water rinse at 18 MΩ·cm with overflow 20 L/min for 20 min before transfer. Residual potassium is verified by inductively coupled plasma mass spectrometry on a droplet extract; the acceptance limit is ≤ 1 × 1012 atoms/cm² for front-end compatibility.
| Etching system | Typical operating condition | Si(100) removal rate | Profile | Primary restriction |
|---|---|---|---|---|
| KOH anisotropic etchant | 30 wt%, 80 °C | 0.8–1.6 µm/min | Anisotropic | Not CMOS-compatible, attacks Al |
| TMAH | 25 wt%, 80 °C | 0.4–1.0 µm/min | Anisotropic | Lower rate, attacks Al unless silicon-saturated |
| HNA | HF:HNO3:CH3COOH, 20–30 °C | 1–50 µm/min | Isotropic | Low SiO2 selectivity, high vapor hazard |
| XeF2 vapor etch | 2–6 Torr, 20–40 °C | 1–10 µm/min | Isotropic | Condensation byproducts, requires vacuum cluster |
Storage at 15–30 °C in the original sealed container prevents carbon dioxide absorption and carbonate residue formation. The product must be segregated from mineral acids, oxidizing agents, aluminium dust, and halogenated solvents. Waste neutralization uses pH-controlled tanks with continuous mixed-bed monitoring; the exothermic dilution of 45 wt% KOH requires the etchant to be added to water, never water to concentrate. For critical cavity geometries, a fresh-bath qualification lot is run with a full wafer-map thickness measurement on 25 points after an initial conditioning etch of 20 µm; this conditions the tank and removes surface contaminants from the recirculation loop. The operational window is closed when the Si(100) monitor rate falls below 0.7 µm/min at 80 °C or when particles ≥ 0.5 µm exceed 500 counts/mL in the recirculation line.
