EL-grade SiC substrate polishing slurry is specified for direct contact with silicon carbide wafer surfaces where large-particle tail, trace metal contamination, pH drift, and lot-to-lot removal rate stability are controlled at semiconductor chemical grades. The downstream application set is separated by process position in SiC wafer manufacturing rather than by generic industrial abrasion category.

The largest consumption of EL-grade slurry is final Si-face chemical mechanical polishing of 100 mm and 150 mm 4H-SiC wafers exiting fixed-abrasive diamond polishing. Slurry at this process position is usually a colloidal silica dispersion with median particle size between 40 nm and 80 nm measured by dynamic light scattering per ISO 22412:2017. Some formulations incorporate a minor fraction of 5–20 nm nanodiamond at weight ratios between 1:0.02 and 1:0.15 relative to silica in order to preserve mechanical action on the Si-face, although nanodiamond increases the risk of microscratching if the large-particle tail is not controlled at point of use. Solids loading is typically 2 wt% to 20 wt%; low-solids formulations below 5 wt% are preferred where pad glazing and recirculation-loop stability are more critical than raw removal rate. pH control splits into alkaline silica systems held at pH 10.0–10.8 by NaOH or KOH titration and acidic oxidizer systems held at pH 2.5–3.5 when hydrogen peroxide or permanganate-based oxidation pathways are selected. The CMP process runs on a single-side polisher with a hard polyurethane pad of Shore D 60–75, platen pressure 3–6 psi (20.7–41.4 kPa), and relative velocity 0.3–1.0 m/s. Material removal rate on Si-face is commonly 0.1–1.2 µm/h; the target is not maximum removal but edge-uniform removal with total thickness variation below 1.5 µm and local roughness Ra 0.10–0.20 nm over a 5 µm × 5 µm AFM scan per ISO 25178-2:2021. The terminal wafers enter epitaxial growth of 650 V, 900 V, and 1,200 V SiC MOSFETs and junction barrier Schottky diodes used in traction inverters, onboard chargers, and photovoltaic string inverters. Wetted distribution materials are limited to polypropylene or PVDF because alkaline silica slurry attacks the passive oxide surface of stainless steel and releases iron contamination; pH drift exceeding 0.3 units in recirculation loops increases large-particle counts and post-clean defect density.

What Limits Subsurface Damage Removal After Fixed-Abrasive Grinding?

After wire sawing and fixed-abrasive diamond grinding, the wafer moves into damage-removal polishing before final Si-face CMP. The depth of grinding-induced damage governs how much material must be removed in this application. If the grinding wheel uses 10–30 µm diamond grit, the subsurface damage layer is typically 1–5 µm; with finer 1–3 µm diamond finishing wheels, the damage depth can be reduced to 0.3–1.0 µm, but wheel loading and cycle time increase. A two-step slurry sequence is generally applied. The first damage-removal CMP step uses either silica blended with nanodiamond at 0.1–0.5 wt% nanodiamond or an alumina-rich slurry in an acidic regime of pH 2–4 to maintain a removal rate of 0.5–2.0 µm/h; the second final-polish step uses colloidal silica at pH 10–11 to remove subsurface amorphization and reduce roughness to Ra 0.05–0.20 nm at 5 µm × 5 µm AFM scan. This staged approach is preferred because single-slurry polishing with only alkaline silica cannot remove deep diamond-induced damage at economical wafer throughput. Production CMP tools for this stage require in situ pad conditioning at intervals of 10–30 min; when pad conditioning is delayed beyond 60 min, removal rate can fall by up to 30% and wafer-to-wafer nonuniformity increases. The acceptance test is not solely AFM roughness. In high-volume manufacturing, witness wafers are etched in molten KOH at 350°C for 3–5 min and etch pit density is counted to confirm that brittle subsurface damage has been removed. The terminal product after this operation is a damage-free wafer for final epitaxy-ready polishing or for direct metrology screening.

Backside Thinning and Interface Thermal Resistance in Power Modules

Backside C-face polishing after wafer thinning is a distinct application because the process must preserve frontside device structures and still remove grinding damage that increases backside ohmic contact resistance. After mechanical thinning to die thickness targets of 80–180 µm, the C-face exhibits grinder swirl, microcracks, and work-hardened subsurface layers that reduce nickel silicide adhesion and raise junction-to-case thermal resistance. EL-grade slurry used here is a silica-based formulation with solids loading 3–10 wt% and pH controlled between 8.0 and 10.5; the lower solids loading reduces pad glazing when soft subpads are used to protect the wafer frontside through a temporary bonding layer. C-face removal proceeds under platen pressure of 1.5–4.0 psi (10.3–27.6 kPa), lower than Si-face CMP because C-face oxidation is faster and can generate edge-fast removal if pressure is excessive. Target backside roughness is Ra 0.2–0.8 nm over a 5 µm × 5 µm AFM scan, measured before backside metallization; the surface must also pass total thickness variation and die flatness limits defined in the device fab assembly specification. Terminal products are thinned die for 1,200 V and 1,700 V power modules in electric vehicle traction inverters, railway converters, and high-power DC-DC converters. Operational boundaries include temporary adhesive compatibility: strongly alkaline pH above 10.5 degrades certain UV-curable thinned-wafer tapes and can cause premature debonding before final cleaning. Slurry filtration at 0.5 µm point-of-use is mandatory because backside scratches cannot be visually distinguished from contact metal defects during post-metal inspection.

When 200 mm SiC Wafers Enter Double-Side Polishing

Double-side polishing becomes a distinct application when wafer diameter moves from 150 mm to 200 mm and both wafer faces must be simultaneously planarized to control bow, warp, and nanotopography. In a double-side polisher, the wafer sits inside a geared carrier plate between upper and lower rotating platens; slurry is supplied through center distributor holes or slurry grooves. The EL-grade slurry used for double-side polishing is usually the same colloidal silica chemistry as final single-side CMP but with solids loading reduced to 2–8 wt% because the two-face polishing interface retains slurry longer and increases particle residence time. Process pressure is applied from both sides at 1.5–3.0 psi (10.3–20.7 kPa) to avoid carrier deformation and wafer fracture, especially on wafers thinner than 350 µm. The geometry target for a 200 mm wafer is total thickness variation below 1.0 µm, bow below 20 µm, warp below 30 µm, and both-face roughness below 0.3 nm Ra; these values are cross-checked against the appropriate thickness and diameter class in SEMI M55. Large-particle control is stricter than in single-side polishing because one aggregate particle can create a scratch on two surfaces that is counted as two defects in post-polish laser inspection. Point-of-use filtration is normally set at 0.2 µm for double-side lines. Terminal products are both-side polished 200 mm SiC wafers for high-volume power device fabs and semi-insulating RF device fabs. Carrier insert wear is a known production failure mode: after 200–500 wafer passes, enlarged insert pockets permit wafer edge roll-off greater than 2 µm, which is detected by double-sided stylus profilometry and corrected by insert replacement or reconditioning.

RF GaN-on-SiC Morphology Is Defined Before MOCVD

For semi-insulating 4H-SiC substrates used in GaN high-electron-mobility transistors, the Si-face surface is the template for AlN nucleation and AlGaN strain modulation. This application requires EL-grade slurry with exceptionally low alkali and transition metal contamination because residual sodium, potassium, calcium, and iron on semi-insulating substrates can diffuse into the GaN buffer and create sheet carrier nonuniformity in the finished transistor. Transition metal lot acceptance is typically tightened below 10 ppb for this grade. The final polishing step is a low-pressure touch polish using soft pads with Shore D 55–65, platen pressure 2–4 psi (13.8–27.6 kPa), and a removal rate below 0.3 µm/h. The objective is local RMS roughness of 0.05–0.15 nm on a 5 µm × 5 µm AFM scan and suppression of micro-scratches that influence step-bunching during MOCVD growth. Slurry filtration at 0.2 µm is typical, and the slurry formulation excludes amine-based additives because trace amines can persist after post-polish cleaning and degrade the subsequent MOCVD interface. Terminal products are epitaxial wafers for RF GaN-on-SiC power amplifiers in 5G macrocell base stations, phased-array radars, and satellite communication transceivers. Polishing lines used for RF wafers are typically segregated from power device slurry loops to prevent cross-contamination by nanodiamond-containing slurries.

Reclaim processing of SiC monitor and dummy wafers is a smaller-volume application but uses slurry under more variable incoming surface conditions. Reclaim wafers arrive with residual oxide hard masks, implanted layers, or defective epitaxial films after device fabrication or process qualification. The slurry sequence on reclaim lines often differs from prime wafer processing: a pre-reclaim step with higher nanodiamond content and pH between 4 and 6 removes residual hard mask oxides and surface films, while a final colloidal silica CMP step restores surface roughness to below 0.3 nm Ra on a 5 µm × 5 µm AFM scan. Slurry changeover on reclaim tools must be controlled because mixed abrasive populations, especially silica and nanodiamond, can aggregate when pH rises above 8; a batch of aggregated slurry produces visible scratches and high laser surface inspection defect counts on subsequent wafers. Published data for specific SiC reclaim configurations is limited, but industrial practice requires designated slurry loops and accelerated filter replacement because mixed device residues are more difficult to clear than prime wafer surfaces. The terminal product is a repolished monitor or dummy wafer used for furnace deposition qualification, implant monitoring, or particle testing.