| HS Code | 238188 |
| Product Name | Selective Si Etchant Electronic/EL Grade |
| Product Type | High-purity selective silicon etchant for semiconductor and electronic applications |
| Chemical Composition | Mixture of hydrofluoric acid, nitric acid, acetic acid, and deionized water |
| Appearance | Clear colorless liquid |
| Physical State At 20 C | Liquid |
| Odor | Sharp, pungent acidic odor |
| Ph | Less than 1 |
| Specific Gravity | Approximately 1.15 at 25°C |
| Boiling Point | Approximately 110°C |
| Freezing Point | Approximately -20°C |
| Vapor Pressure | Moderate at room temperature |
| Solubility In Water | Fully miscible |
| Purity Grade | Electronic/EL grade |
| Etch Selectivity | Formulated to etch silicon selectively with controlled removal and reduced attack on select non-silicon materials |
| Silicon Etch Mechanism | Nitric acid oxidizes silicon, hydrofluoric acid removes the resulting silicon oxide layer |
| Storage Temperature | 15°C to 30°C |
| Shelf Life | Typically 6 to 12 months under sealed and recommended storage conditions |
As an accredited Selective Si Etchant Electronic/EL Grade factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.
| Packing | Selective Si Etchant Electronic/EL Grade, packaged in a 1-gallon HDPE bottle with secure seal, ensures purity and safe handling. |
| Container Loading (20′ FCL) | 20' FCL: palletized drums securely braced and labeled, compliant with hazardous goods regulations for Electronic/EL Grade Selective Si Etchant. |
| Shipping | Selective Si Etchant Electronic/EL Grade ships as a hazardous, corrosive liquid. Ground transport only, per DOT/UN rules. Use leak-proof, UN-approved containers with secure cushioning, and proper corrosion/etchant hazard labels. Avoid incompatible materials. Ensure trained personnel handle, document, and ship with appropriate dangerous-goods paperwork. |
| Storage | Store in a tightly sealed original container in a cool, dry, well-ventilated area away from direct sunlight, heat, and moisture. Keep segregated from incompatible materials such as bases, metals, and oxidizers. Use corrosion-resistant secondary containment. Maintain temperatures between 15–25°C, avoiding freezing. Ensure proper labeling and restricted access. |
| Shelf Life | Shelf life is typically six months from manufacture when stored sealed, cool, and protected from light and contamination. |
In multi-crystalline photovoltaic wafer manufacturing, saw-damage removal and formation of a low-reflectance isotropic texture are executed with an Electronic/EL Grade selective silicon etchant based on 49 wt% HF, 70 wt% HNO3, and deionized water. The feed blend is maintained at volumetric ratios between 1:3:1 and 1:4:2 HF:HNO3:H2O; acetic acid may replace a portion of the water at 1:3:2 to moderate nitrous acid generation and improve surface wetting. Inline acid texturing lines run at 6 °C to 14 °C with bath temperature controlled to ±0.5 °C; etch removal is typically 4–8 µm per side at an etch rate of 1–2 µm/min. Recirculation, filtration through 0.2 µm PVDF cartridges, and continuous replenishment by titration and specific gravity are standard on production lines. The exothermic HNO3 reduction requires exhaust scrubbing for HF and NOx; above 18 °C the reaction can shift toward porous silicon formation and nonuniform reflectance. Incoming acids are controlled under SEMI C27 and SEMI C28; finished modules are qualified under IEC 61215-2:2021. Terminal product types are multi-crystalline silicon photovoltaic cells and framed or frameless PV modules.
Silicon wafers thinned to 100–250 µm after backgrinding carry subsurface microcracks that reduce die fracture strength. An Electronic/EL Grade selective silicon etchant removes 20–50 µm of backside silicon in a single-wafer spin processor at 20–30 °C; typical volumetric feed ratios are 1:3:1 to 1:6:2 HF(49 wt%):HNO3(70 wt%):H2O or acetic acid, adjusted to etch rates of 3–15 µm/min. The process conflict is preservation of frontside passivation and thermal oxide while aggressive silicon dissolution proceeds; selectivity depends on the HNO3-to-HF ratio, dispense temperature, and wafer rotation speed. Exposed aluminum pads are incompatible with HF-containing etchant and require frontside protection or post-etch deprocessing. Silicon thickness is monitored by IR interferometry after spin drying. Chemical purity is governed by SEMI C27 and SEMI C28; final package reliability is tested under JEDEC J-STD-020E, and die strength under MIL-STD-883J TM 2019.9. Single-wafer tools with PFA dispense lines and infrared pyrometry hold the reaction layer within ±1 °C of setpoint because etch rate shifts become observable above 30 °C. Terminal product types are thinned memory die, stacked logic packages, and power management wafers.
Exposure of via tips after backgrinding is performed with an Electronic/EL Grade selective silicon etchant that removes backside silicon around the vias to generate controlled protrusion for subsequent metallization. A volumetric feed ratio of 1:4:3 to 1:6:2 HF(49 wt%):HNO3(70 wt%):DI water is used at 18 °C to 25 °C, producing etch rates of 2–8 µm/min; final via protrusion is targeted at 0.5–1.5 µm. Overetch is kept below 15% of the target protrusion because additional removal undercuts the via liner oxide and modifies the wetting profile of the subsequent dielectric passivation. Single-wafer spray etchers with optical endpoint detection and white-light interferometry are used, with wafer mapping at not fewer than 9 measurement points to detect die-level nonuniformity. Incoming etch components conform to SEMI C27 and SEMI C28; thermal cycling qualification follows JEDEC JESD22-A104E. Terminal product types include TSV interposers, 3D stacked DRAM packages, and high-bandwidth memory stacks.
In silicon piezoresistive pressure sensor and MEMS microphone fabrication, a cavity or diaphragm is defined by patterned Si3N4 or SiO2 hardmask and released with an Electronic/EL Grade isotropic silicon etchant. The volumetric blend is typically 1:3:2 to 1:5:2 HF(49 wt%):HNO3(70 wt%):CH3COOH(99.8 wt%), maintained at 22 °C ± 1 °C in a recirculated PFA bath; etch rate is held between 1 µm/min and 3 µm/min. Mask selectivity is verified on pilot wafers by ellipsometric measurement of dielectric loss after half of the target cavity depth; lateral undercut of the hardmask is kept below 0.2 µm per side for diaphragm feature sizes below 50 µm. Hydrogen bubbles generated during Si dissolution can locally suppress etching in deep cavities, so wafer carriers are agitated at 10–20 cycles/min without surfactant. The chemistry is governed by SEMI C27 and SEMI C28; cleanroom operation follows ISO 14644-1 Class 5; automotive MEMS final qualification follows AEC-Q100 Rev H. Terminal product types are pressure sensor dies, MEMS microphone backplates, accelerometer proof masses, and inkjet nozzle membranes.
Carrier wafer removal in fan-out wafer-level packaging relies on selective dissolution of a silicon carrier after epoxy mold compound encapsulation and redistribution-layer formation. The etchant is supplied as Electronic/EL Grade with a volumetric feed ratio of 1:3:1 to 1:5:1 HF(49 wt%):HNO3(70 wt%):DI water, operated at 25 °C to 35 °C; dissolution rates for single-crystal carrier silicon are 5–20 µm/min. The process window is bounded by complete silicon removal on one side and by the need to avoid leaching exposed Cu pillars, solder masks, or mold compound on the other; endpoint detection by IR interference or mass loss is used, with an overetch not exceeding 10% of the measured carrier thickness. Spray or immersion equipment with PFA piping, HF/NOx abatement, and DI water rinse followed by N2 spin drying is standard. Chemical purity is controlled under SEMI C27 and SEMI C28; package moisture sensitivity and thermal cycle reliability are tested under JEDEC J-STD-020E and JESD22-A104E. Terminal product types are fan-out wafer-level packages, panel-level embedded die modules, and system-in-package units.
For silicon-based diagnostic cartridges and lab-on-chip devices, microfluidic flow channels are created by timed isotropic etching through a hardmask. The Electronic/EL Grade silicon etchant is fed at a volumetric ratio of 1:2:1 to 1:3:2 HF(49 wt%):HNO3(70 wt%):CH3COOH(99.8 wt%), with bath temperature controlled at 18 °C to 24 °C; etch rates of 1–4 µm/min are typical for patterned wafers. Channel depth is usually 10–100 µm, and lateral etch bias is controlled by hardmask composition; LPCVD Si3N4 masks exhibit lower undercut than wet thermal SiO2 under identical conditions. For channels narrower than 20 µm, dummy fill and symmetrical mask openings are used to equalize hydrodynamic supply of fresh etchant across the wafer; otherwise, inner-to-outer die etch-depth variation exceeds ±3%. The etchant components are specified under SEMI C27 and SEMI C28; medical diagnostic devices are manufactured under ISO 13485:2016 quality management. Terminal product types include lab-on-chip cartridges, point-of-care diagnostic chips, and DNA sequencing flow cells.
Competitive Selective Si Etchant Electronic/EL Grade prices that fit your budget—flexible terms and customized quotes for every order.
For samples, pricing, or more information, please contact us at +8615365186327 or mail to admin@ascent-chem.com.
We will respond to you as soon as possible.
Tel: +8615365186327
Email: admin@ascent-chem.com
Flexible payment, competitive price, premium service - Inquire now!
Selective Si Etchant Electronic/EL Grade, procurement designation SSE-EL-100, is a filtered isotropic silicon removal bath formulated from electronic-grade hydrofluoric acid, nitric acid, and acetic acid with a controlled low-particulate diluent. The product is supplied as a single-phase, colorless to pale-yellow liquid with a density of 1.13–1.18 g/mL at 20 °C and a boiling point consistent with mixed-acid systems above 90 °C. Unlike buffered oxide etch or dilute HF formulations that remove silicon dioxide, this bath operates in the high-HNO3 domain: nitric acid oxidizes silicon to SiO2, and hydrofluoric acid dissolves the generated oxide, leaving thermal SiO2 at a significantly lower removal rate.
Electronic/EL grade denotes a trace impurity envelope rather than a general-purpose etch rate claim. Component acids are screened against SEMI C27, SEMI C29, and SEMI C35 for electronic-grade hydrofluoric acid, nitric acid, and acetic acid respectively. The blended product is filtered through 0.05 µm PTFE membranes and packaged in fluoropolymer containers within an ISO 14644-1 Class 5 cleanroom. Each lot is released with a certificate of analysis covering a 26-element panel by ICP-MS using matrix-matched calibration and internal standardization. Packaging is offered in 2.5 L and 10 L PFA containers; the 10 L container is fitted with a nitrogen pressure dispensing head to limit atmospheric moisture uptake.
| Parameter | Method | Specification |
|---|---|---|
| Sodium, potassium, calcium, magnesium | ICP-MS | ≤ 1 ppb each |
| Iron, copper, nickel, chromium | ICP-MS | ≤ 1 ppb each |
| Aluminum, zinc | ICP-MS | ≤ 5 ppb each |
| Total trace metal impurities | ICP-MS | ≤ 20 ppb |
| Chloride | Ion chromatography | ≤ 2 ppm |
| Sulfate | Ion chromatography | ≤ 5 ppm |
| Particle count ≥ 0.2 µm | Laser particle counter calibrated to ISO 21501-3 | ≤ 50 particles/mL |
| Particle count ≥ 0.5 µm | Laser particle counter calibrated to ISO 21501-3 | ≤ 10 particles/mL |
Selective silicon removal is governed by the ratio of nitric acid to hydrofluoric acid and by the concentration of acetic acid, which moderates nitric acid dissociation and reduces SiO2 attack. In baths formulated with HNO3:HF above 5:1, thermal oxide etch rate remains below 0.05 µm/min while Si(100) removal proceeds above 0.8 µm/min. At ratios below 4:1, selectivity collapses because HF-dominated dissolution attacks both silicon and silicon dioxide. Batched tolerances are therefore maintained within ±0.2 ratio units to avoid a selectivity cliff-edge.
Temperature is the primary production risk. A recirculating bath equipped with a fluoropolymer heat exchanger and thermocouple feedback maintains 20 °C ± 1 °C. Etch rate rises by approximately 2.5× per 10 °C increase over the 15–35 °C range, so an uncontrolled 3 °C excursion shifts removal by more than 15%. In a stand-alone wet bench with PVDF recirculation and 0.1 µm point-of-use filtration, witness-wafer etch rate drift over 8 h was held to 6% when the bath was replenished at 1% of initial volume per hour. Without replenishment, H2SiF6 accumulation and nitric acid depletion increased critical dimension loss variability.
| Process parameter | Typical value or range |
|---|---|
| HNO3:HF volume ratio | 7.0:1 ± 0.2 |
| Acetic acid fraction | 15–20 vol% |
| Temperature set point | 20 °C ± 1 °C |
| Si(100) etch rate | 0.9–1.4 µm/min |
| Thermal SiO2 etch rate | 0.02–0.05 µm/min |
| Selectivity Si:SiO2 | 40:1 to 60:1 |
| Temperature coefficient | 2.5× per 10 °C in 15–35 °C |
| Silicon loading limit | 5 g/L total dissolved silicon |
Processing of MEMS sacrificial silicon, polysilicon over oxide, and wafer thinning is typically executed in immersion mode with wafer carriers made of PVDF or PFA. Single-wafer spin processing is not recommended because the vapor phase and droplet acceleration alter local HNO3 concentration. Production wafers are pre-cleaned in dilute HF and rinsed in deionized water before immersion to minimize native oxide variability. A post-etch overflow rinse is followed by an isopropanol vapor dry. For high-aspect-ratio cavities, the isotropic etch produces lateral undercut approximately equal to the vertical silicon removal. Dimensional control is therefore specified by a budgeted lateral over-etch of 1.1–1.3× the target thickness for flat cavities. When vertical removal exceeds 10 µm, the etch is interrupted at 50% of the target, rinsed, inspected for residue, and resumed only after confirmation of thermal oxide integrity. Published data for high-aspect-ratio cavity etching in EL-grade HNA are limited; process development should include witness-wafer measurements on every bath change.
Because the formulation is incompatible with borosilicate glass and stainless steel, wetted components are limited to PTFE, PFA, PVDF, and semiconductor-grade polypropylene. Polypropylene is restricted to ambient storage because mixed-acid vapor pressure at 35 °C accelerates oxidative embrittlement. The bath must be exhausted through acid-resistant ducting with a face velocity of at least 0.5 m/s at the wet bench sash. Spent etchant containing more than 5 g/L dissolved silicon should be treated as fluoride-bearing hazardous waste and neutralized with calcium hydroxide slurry to precipitate CaF2. On-site distillation or regeneration of the bath is not recommended.
Compared with TMAH or KOH anisotropic silicon etchants, SSE-EL-100 does not produce crystal-plane-dependent slopes; it removes silicon isotropically and produces smooth hemispherical recesses on Si(100) with surface roughness below 2 nm Ra after 5 µm removal. Alkaline etchants require temperatures above 80 °C, introduce alkali-metal cations that degrade gate oxide integrity, and attack aluminum metallization. This HNA bath operates at ambient temperature and its trace metal controls make it suitable for front-end sacrificial polysilicon release before metallization. However, the bath is not selective to p-doped or n-doped regions and cannot replace TMAH for through-wafer vias requiring 54.7° sidewall angles.
Relative to technical-grade HNA mixtures, the Electronic/EL Grade differs in three measurable parameters: trace metal ceiling, particle count, and lot-to-lot ratio tolerance. Technical-grade mixtures may contain iron above 100 ppb and copper above 50 ppb depending on raw acid sources, whereas the EL grade is released below 1 ppb for Fe and Cu. Particle counts in technical-grade materials may exceed 103 mL−1 for particles ≥ 0.2 µm, compared with 50 mL−1 for this product. The volumetric HNO3:HF ratio in ungraded mixtures is often specified as a nominal recipe without batch-specific titration; the EL product is released with titrated ratios and adjusted with low-metal diluent.
Against vapor-phase XeF2 etching, which removes silicon selectively without attacking SiO2, the liquid HNA formulation provides higher etch rate and batch wafer throughput but introduces acid handling and isotropic etch control constraints. XeF2 is typically operated at 1–3 Torr with cycle times of tens of seconds, but its silicon etch rate may remain below 0.5 µm/min per cycle and chamber residues require periodic fluorine plasma cleaning. The liquid product is preferred when production volume requires parallel batch processing of 25 wafers per carrier rather than vacuum chamber loading. This product is not a buffered oxide etch; it intentionally minimizes oxide removal. Where high-rate thermal SiO2 or TEOS etching is required, buffered HF or vapor HF systems remain the appropriate alternatives.
