Within 300 mm front-end lines running shallow trench isolation and interlayer dielectric planarization, the electronic/EL grade retaining ring polishing pad operates as a sacrificial planarization interface between the carrier ring and the pad stack. The wafer carrier ring—typically unfilled PEEK or PPS with a flatness tolerance of ±5 µm across the bond line—is dressed against the ring pad before production lot start. The pad compound is specified at 62–68 Shore D per ASTM D2240-15, with closed-cell pore diameter 25–45 µm and density 0.68–0.85 g/cm³ per ASTM D792-20; this range prevents platen-induced ring vibration while limiting pad glazing under oxide slurry exposure. The standard slurry recipe for ring break-in is 2.0–5.0 wt% fumed silica dispersed in deionized water, pH adjusted to 10.2–11.1 with KOH, with no additional abrasive loading when the pad is conditioned ex situ; H₂O₂ is excluded from the ring-polish step because copper interconnect exposure is not intended at this stage. The process is run on four-zone air-backed 300 mm CMP heads at platen speed 85–97 rpm, head speed 80–90 rpm, downforce 3.0–4.5 psi, and slurry flow 120–180 mL/min; edge pinch-off caused by over-dressing is monitored by acoustic emission sensors. Pad grooves are maintained at depth 0.5–0.8 mm and pitch 1.5–2.5 mm, with ex situ conditioning using a 200 µm CVD diamond disk at 2.5–4.0 lbf/in² for 30–45 min before lot start. Compliance is validated against SEMI S2-0718 for equipment-associated consumable safety, SEMI S8-0718 for tool ergonomics during pad changeover, ISO 14644-1:2015 Class 4 cleanroom compatibility, and REACH Annex XVII restricted substances. The terminal output is a planarized 300 mm device wafer lot with post-polish within-wafer nonuniformity below 3% 1σ, and the pair of retaining rings returned to production with a flatness re-qualification of ≤ 5 µm.

Groove Depth Tolerance in Polishing-Pad Converting Lines

Serious groove-depth drift on converted pads is typically traced to inadequate laser focus control or to release-liner adhesive migration into the foam cell walls, not to the base polymer. In this downstream segment the electronic/EL grade sheet is converted for OEM and aftermarket retaining-ring pad programs. The grade is transferred as 100% solid polyurethane sheet without additional plasticizer or filler; if a two-component polyurethane laminating adhesive is used, its mix ratio is 100:5–100:10 resin to hardener by weight. The forming process starts with roll stock at thickness 0.8–3.0 mm and width 1.0–1.4 m; adhesive lamination uses an acrylic transfer film at 15–25 g/m² dry coat weight, pressed at 2–4 kg/cm² and 25–35 °C, followed by 24 h dwell before die cutting. Grooves are machined by CO₂ laser at 10.6 µm wavelength, 120–180 W, scan speed 8–12 m/min; groove depth tolerance is held at ±0.05 mm and groove pitch at 1.5–3.0 mm. Die-cut final parts are held to ±0.2 mm outer diameter tolerance and inspected under 10× magnification for adhesive squeeze-out. Compliance for the converted article is documented against RoHS 2011/65/EU Annex II, REACH Article 33 SVHC disclosure, ISO 9001:2015 for lot traceability, and ASTM D638-14 tensile elongation for the film-laminated stock. The terminal product types include die-cut 304 mm ring pads, pre-grooved ring-polish pads for 200 mm CMP tools, and adhesive-backed ring pad kits supplied to equipment refurbishers.

Reclaim operations processing PEEK retaining rings for copper/low-k tools must resolve a process conflict between pad hardness and ring wear: a pad below 55 Shore D produces ring edge rounding, while a pad above 75 Shore D raises local contact stress and risks sub-surface cracking in recycled rings that have absorbed CMP slurry acids. The electronic/EL grade is specified at 58–70 Shore D for this line. The ring-polish slurry is formulated with 1.0–2.5 wt% colloidal silica, 0.5–2.0 wt% H₂O₂, 0.5–1.5 wt% glycine, and 0.005–0.050 wt% benzotriazole at pH 5.5–7.0; citric acid buffering is used at 0.1–0.5 wt% to suppress local pH spikes caused by copper dissolution. Aggressive chelating additives are avoided above 0.5 wt% because they produce ring surface roughening above 0.1 µm Ra. The production process uses a single-side rotary polisher with platen speed 60–90 rpm, head speed 55–80 rpm, downforce 2.5–4.5 psi, and in situ conditioning with a 100 mm CVD diamond disk at 4–6 lbf/in²; pad surface temperature is maintained below 45 °C by chilled slurry return. Qualification of the reclaimed ring includes flatness measurement by laser interferometry to ≤ 11 µm total indicator reading and tensile strength per ASTM D638-14 after 72 h acid immersion. Compliance standards for the operation include SEMI S2-0718, ISO 14644-1:2015 Class 5, and REACH Article 33. The terminal output is a re-qualified PEEK retaining ring set for 300 mm Cu/low-k CMP polishers, with traceable lot-level flatness and no outer-ring chipping above 0.5 mm depth.

When 150 mm SiC Epi-Ready Wafers Require Retaining Ring Flatness Below 3 µm

The process window narrows sharply when 150 mm SiC epi-ready wafers are polished for 1.2 kV MOSFET or Schottky diode production. The ring pad must withstand the high downforce demanded by the C-face removal while limiting pad debris that could scratch the SiC surface. Slurry formulation addition ratios are 0.5–1.5 wt% nano-diamond abrasive with primary particle size 20–50 nm, 1.0–2.0 wt% H₂O₂ as oxidizer, pH 2.0–4.0 adjusted with HNO₃; a polymeric dispersant is added at 0.05–0.15 wt% to prevent diamond agglomeration on the pad. The pad itself is closed-cell polyurethane of hardness 80–90 Shore D per ASTM D2240-15 with pore size 20–40 µm and compressibility below 1.5% at 5 psi. The CMP process runs at platen speed 35–45 rpm, head speed 30–40 rpm, downforce 4.0–7.0 psi, slurry flow 80–120 mL/min, and pad temperature 25–32 °C; the lower platen speed relative to oxide CMP is necessary to reduce shear heating at the pad–ring interface. Published wear-rate data for this exact ring-pad configuration remains limited; qualification runs on production SiC CMP polishers typically rely on lot-level ring flatness data rather than universal kinetic models. High-pH slurries are avoided because ring pad swelling above 2% thickness change shifts groove geometry. Compliance includes SEMI M55 dimensional references for 150 mm SiC wafers, ISO 14644-1:2015 Class 5 cleanroom handling, ASTM D638-14 tensile integrity after acidic slurry exposure, and REACH Annex XVII. The finished products are 150 mm SiC epi-ready wafers with ring-induced edge exclusion below 2 mm and retaining rings re-qualified at flatness ≤ 3 µm.

In 200 mm mature-node fabs, the replacement interval for retaining ring polishing pads is managed by ring flatness drift, not by pad chemistry, and the pad is run with deionized water mist at 0.1–0.3 L/min as the only fluid addition, avoiding slurry entirely; compliance under RoHS 2011/65/EU Annex II and ASTM D2240-15 is documented by the pad supplier, the downstream process is a monthly preventive-maintenance pad swap on a 200 mm CMP polisher at platen speed 70–90 rpm and downforce 2.0–3.0 psi, and the terminal product is a refreshed 200 mm retaining ring set with flatness ≤ 8 µm that returns the mature-node oxide tool to production within a 45 min maintenance window.

What Limits Slurry Transport in Copper Pillar Bump Planarization?

At 25 µm pitch Cu pillar bump layers, the pad-engagement area under the retaining ring is small, and the dominant process constraint is slurry transport across the pad land area. The electronic/EL grade pad is grooved with X-Y or radial patterns at depth 0.4–0.8 mm and land width 1.0–2.0 mm, and it is run with a slurry formulation containing 2.0–4.0 wt% colloidal silica, 0.5–1.5 wt% glycine, 0.5–2.0 wt% H₂O₂, and 0.005–0.020 wt% BTA at pH 6.0–7.5; the addition of 0.1–0.3 wt% polyethylene glycol is used to control pad friction to below 0.35 coefficient. The downstream process sequences copper bulk removal at platen speed 70–110 rpm, head speed 68–100 rpm, downforce 1.5–3.5 psi, then barrier removal with a softer pad grade; in situ conditioning is performed at 3–5 lbf/in² with a 100 µm CVD diamond disk. Compliance for the advanced packaging line includes SEMI S2-0718, SEMI S8-0718, ISO 14644-1:2015 Class 5, and IEC 62474 material declaration. The terminal product is a 300 mm wafer with Cu pillar bumps planarized to within-wafer nonuniformity ≤ 4% 1σ and no pad-induced bump shearing above 0.3 µm height deviation.