On a 300 mm front-end wet bench, polysilicon etchant electronic/EL grade is supplied through a PFA recirculation loop to an immersion tank holding FOUP-compatible cassettes. Bath temperature is maintained at 18°C to 25°C, and the etch time is set from blanket-film removal data generated on furnace-grown polysilicon coupons. The working mixture is formulated from electronic-grade HNO3 (70 wt%), HF (49 wt%), and anhydrous acetic acid at volumetric ratios fixed between 1:2:1 and 1:5:2; the locked ratio is selected after patterned undercut measurements. In gate-last integration, the solution removes sacrificial polysilicon dummy gates and polysilicon test structures without reliance on plasma strip alone. Component trace metals conform to supplier certificates aligned with SEMI C10 for hydrofluoric acid, SEMI C12 for nitric acid, and SEMI C11 for acetic acid; point-of-use particle count is checked with an optical particle counter calibrated to ISO 21501-4. Terminal products from this application segment include logic CMOS devices, DRAM, NAND flash, and microcontroller products. A primary process limitation is the chemical's finite thermal oxide selectivity, since HF in the mixture also etches pad oxide; pre-etch ellipsometry is used to establish the oxide loss allowance for each lot.

What Limits the Etch-Back Window for TOPCon Solar Polysilicon Wrap-Around Removal?

The rear-side tunnel oxide/polysilicon stack in TOPCon cell lines creates parasitic shunting when polysilicon wraps around the wafer edge or deposits on the front textured surface. Wet polysilicon etchants are applied in inline single-wafer spray tools or batch immersion tanks to remove 0.1 µm to 0.5 µm of wrap-around poly-Si while preserving the front emitter. The working bath is typically a dilute HNO3-HF-H2O system, with HNO3:HF volumetric ratios held between 4:1 and 12:1 and water dilution adjusted to suppress porous silicon formation; acetic acid is added at 0.5–1.0 parts against total acid volume in some lines to reduce surface tension defects. Bath temperature is controlled to ±0.5°C because the etch is exothermic and the reaction rate varies with accumulated nitrous acid. Endpoint control relies on inline colorimetry of the spent bath and periodic coulometric thickness verification. Chemical supply is controlled under SEMI C10 and SEMI C12 component specifications for trace metal impurities because front-side emitter contamination reduces implied open-circuit voltage. Terminal products are n-type TOPCon solar cells and modules with bulk resistivity typically in the range of 0.2–0.5 Ω·cm for the cell wafer. Published data for specific inline tool etch uniformity is limited; the dominant production limitation is non-uniform gas evolution causing edge undercut and mask lift.

Where display fabs run low-temperature polysilicon backplanes on Gen 6 glass, the etchant is used after excimer laser crystallization to remove residual crystallized polysilicon from non-device regions and to structure test keys. The bath is qualified on aluminosilicate glass substrates, using a low-flow PFA spray-and-spin processor to limit HF attack on the glass. Composition is adjusted to a lower HF fraction than semiconductor front-end processes, frequently in the volume ratio HF:HNO3:CH3COOH of 1:2:4, with process temperature held at 22°C to 24°C and spin speed from 600 rpm to 1,200 rpm. Etch time is set by measuring sheet resistance change and channel island critical-dimension shift through optical linewidth metrology. The terminal product is a low-temperature polysilicon active-matrix backplane for AMOLED or high-resolution LCD panels. Compliance for display-grade chemistry is referenced to SEMI C10 for fluoride-containing components and to ISO 14644-1 for airborne particulate control at the point-of-use cabinet. Glass attack and molybdenum/aluminum metal line undercut are primary limitations; etch stops are therefore qualified against moly seed layers and buffer oxide layers before production release.

MEMS Sacrificial Polysilicon Release in Surface-Micromachined Sensor Fabrication

Surface-micromachined accelerometers and pressure transducers use polysilicon etchant to remove sacrificial polysilicon or amorphous-silicon layers deposited over phosphosilicate-glass anchors. The etch is carried out after patterning, often in a low-bath-temperature HNO3-HF-CH3COOH mixture with weak agitation to reduce lateral undercut of structural silicon. Ratios are selected near the high-HNO3 region, for example HF:HNO3:CH3COOH at 1:6:3, to maintain isotropic etch character for release of narrow comb-drive gaps. Process temperature is maintained at 20°C ± 0.5°C, and release is monitored by timed etch of an adjacent sacrificial test pad rather than pattern inspection. Following release, wafers enter deionized water rinsing and either isopropyl alcohol/CO2 critical point drying or vapor-phase drying to prevent stiction. Terminal products are automotive inertial sensors, gyroscope ASIC chips, and biomedical MEMS pressure transducers. The etch bath must meet component specifications such as SEMI C10, SEMI C11, and SEMI C12, and the line typically logs sub-0.2 µm particulate contamination before release. A key operational boundary is that wet release is not suitable for structures with narrow gaps below 1 µm when capillary forces cannot be controlled; vapor-phase HF alternatives are used instead.

After blanket polysilicon deposition on monitor wafers, reclaim operations apply the etchant to strip polysilicon film that was deposited for particle monitoring, furnace qualification, or CMP pad qualification. In a Class 1 PFA batch tank, 300 mm wafers are immersed at 20°C to 26°C until the film is visually cleared; the batch then moves to a cascade rinse, an SC-1/SC-2 clean sequence, and final spin drying. Etchant composition is premixed at HF:HNO3:CH3COOH volume ratios from 1:3:2 to 1:4:2, selected to deliver an etch rate of approximately 1–2 µm/min on fine-grained polysilicon and a surface roughness increase below 0.5 nm RMS on the underlying silicon, measured by AFM. Metal contamination after reclaim is verified by TXRF at detection limits below 1×10¹⁰ atoms/cm². The reclaimed substrate returns to production as a monitor wafer, test wafer, or dummy wafer; final products are not shipped to end customers, but the reclaim step reduces virgin test-wafer consumption. Primary process limitation is lot-to-lot polysilicon grain-size variation from the blanket furnace recipe, which can change etch rate by 10–15% and requires coupon tests before each batch.

When Electronic-Grade Polysilicon Etchant Replaces Reagent-Grade Acid in Failure Analysis and Cross-Section Prep

In failure-analysis laboratories, polysilicon etchant is used as a selective delineation solution to reveal grain structure and film interfaces during cross-section preparation. The etch is applied at room temperature with a calibrated micro-pipette or in a small PTFE beaker under a ventilated fume hood; immersion times of 5–30 seconds are controlled by visual inspection of the polysilicon film color change. A typical working ratio is HF:HNO3:CH3COOH of 1:3:3, diluted 1:1 with deionized water to slow the reaction for manual endpoint control. The electronic/EL grade is specified to avoid adding transition-metal contamination that could distort scanning electron microscopy contrast or secondary ion mass spectrometry background. Terminal outputs are polished cross-section samples, plan-view specimens, and delayered devices used for root-cause failure analysis of memory and logic products. Compliance documentation typically includes lot-certified cation analysis by inductively coupled plasma mass spectrometry and particle counts per SEMI C10. Operational boundary: prolonged exposure above 25°C causes thermal oxide undercut and should be avoided when imaging gate oxide interfaces.