Aluminium Wet Etchant Blends for Thin-Film Transistor Metallization

In thin-film transistor LCD fabrication, EL-grade phosphoric acid serves as the bulk acid reservoir in aluminium etchant blends used to pattern gate and source-drain electrodes on glass substrates. A production-qualified baseline is 72–78 vol% H3PO4 at 85% assay, 3–5 vol% HNO3 conforming to SEMI C35, 8–12 vol% CH3COOH, and the balance deionized water. The nitric acid oxidizes the aluminium surface to Al2O3 within 0.5–2 s of contact; phosphoric acid then dissolves the oxide, while acetic acid controls wetting and reduces interfacial attack at the grain boundaries. Bath temperature is held at 35–42°C in an inline spray etch chamber with dual-fluid nozzles operating at 1.0–1.5 kgf/cm², and the etch rate for Al-0.5% Cu films is typically 0.4–0.8 µm/min at 40°C. The specific rate depends on grain size, copper precipitation state, dissolved aluminium loading, and agitation across the Gen-6 glass sheet. Endpoint detection is based on laser reflectivity at 590 nm and is set to stop within ±1 s of the nominal breakthrough to avoid overetch of the underlying barrier metal.

The process window is narrow because excess HNO3 accelerates undercut at the aluminium/barrier interface, while insufficient HNO3 leaves copper or neodymium residues at alloy grain boundaries. For a 3 µm line/space pattern on Al-Nd alloys, the HNO3 concentration in the bath is controlled within ±0.2 vol% and the temperature within ±0.5°C. Dissolved aluminium build-up above 5000 ppm suppresses etch rate and shifts the endpoint signature, so a feed-and-bleed rate of 0.2–0.5 L/min per 100 L bath volume is used. The EL-grade acid must meet SEMI C36 for trace metal impurities; Fe and Cu above 50 ppb in the bath can alter the galvanic potential at grain boundaries and produce post-etch residues requiring a second cleaning step. The terminal products are thin-film transistor source-drain electrodes, gate fan-out lines, and redistribution wiring used in display modules that later pass EU RoHS 2011/65/EU assembly verification.

Hot phosphoric acid stripping of silicon nitride after junction formation relies on liquid-phase selectivity rather than plasma damage control, and the working bath is not a minor additive but the main etch medium. The as-received 85% electronic-grade acid is heated to 150–160°C in a quartz or PFA-lined reflux tank; at this temperature the etch rate for low-pressure CVD silicon nitride is approximately 4–7 nm/min, while thermal silicon dioxide removal remains below 1 nm/min. The temperature must be stable within ±1°C because a drop below 145°C reduces SiN etch rate below process throughput limits, while a rise above 165°C accelerates dehydration of phosphoric acid to polyphosphoric species and shortens bath life.

The selectivity window is realised only after the bath is seasoned with dissolved silica at 100–500 ppm as SiO2, which suppresses oxide attack by shifting the dissolved silicic acid equilibrium. Some high-volume fabs use proprietary silicon-doping additives that hold the SiN:SiO2 selectivity at 30:1 to 50:1 for batch runs of 24–48 h. Bath replenishment is governed by density rather than pH; the specific gravity is maintained at 1.70–1.72 g/mL at 25°C by controlled DI water addition to compensate for evaporative loss. Particle control is verified by a laser particle counter calibrated to ISO 21501-4, with a typical acceptance limit of ≤10 particles/mL at ≥0.2 µm.

The dominant operational boundary is fluoride contamination carried over from prior HF-based oxide etching. A fluoride spike of 100–200 ppb can increase silicon dioxide etching by one order of magnitude and collapse the SiN:SiO2 selectivity within a single batch. The terminal features are patterned silicon nitride spacer and hard-mask layers removed after source/drain implant activation in logic and memory devices at 28 nm and above design rules. Published data for the exact bath lifetime at sub-10 nm nodes is limited because foundries treat the seasoning and replenishment profiles as process-specific intellectual property.

Why Does Phosphoric Acid Loading Shift Indium Tin Oxide Undercut in OLED Patterning?

Indium tin oxide wet patterning on OLED anodes requires an acid mixture that removes amorphous ITO at 0.2–0.6 µm/min without attacking the underlying Mo/Al/Mo data bus. EL-grade H3PO4 is added at 5–15 vol% to a hydrochloric acid/nitric acid base, and the bath is applied in a single-wafer puddle tool at 32–38°C. The phosphoric ion forms a low-solubility interfacial layer on exposed molybdenum and aluminium during puddle development, reducing galvanic undercut from more than 2 µm to below 0.5 µm on 3 µm line/space test structures. The etch profile is controlled by acid mixing order rather than by total acidity; H3PO4 must be pre-diluted in the organic acid phase before nitric acid addition to avoid local heating and vapour emission at the mix tank. Endpoint is triggered by optical emission at 590 nm, but the endpoint signal must be compensated for dissolved indium loading above 30 mg/L, at which point the sidewall slope angle shifts from 45–60° to below 30°.

The H3PO4 loading must be held within ±0.5 vol% because lower levels increase undercut and higher levels leave tin phosphate residues that require a separate alkaline clean. If the EL-grade acid contains Fe above 20 ppb, it catalyses decomposition of any residual hydrogen peroxide in the rework bath, generating bubble defects in fine channel areas. The acid is released only after SEMI C36 trace-metal verification by ICP-MS, with particular attention to Fe, Cu, and Ni because these metals can plate onto exposed ITO and form micro-masks. The terminal products are OLED anode strip patterns on Gen-6 half-cut sheets and capacitive touch sensor bridges used in modules certified under IEC 62341-1 for display performance. The acid does not remain in the final device; its anionic residue is removed in the subsequent DI rinse and dry sequence.

The compliance checklist matrix below consolidates the incoming acid requirements and process boundaries for the downstream routes discussed.

When gallium arsenide gate recess is performed with a peroxide-containing acid mixture, the bath temperature must remain below 25°C because hydrogen peroxide decomposition accelerates above 30°C. A standard H3PO4:H2O2:H2O volume ratio of 1:1:25 removes GaAs isotropically at 0.8–1.5 µm/min at 23°C, while a 1:1:10 mixture is used for indium phosphide mesa structures where the oxide dissolution step is slower. The H2O2 oxidizes the III-V surface to Ga2O3/As2O3 or In2O3, and the EL-grade phosphoric acid dissolves the oxide, producing a sidewall radius approximately equal to the vertical etch depth. The acid mixture is prepared in a jacketed ETFE recirculation tank with inline particle filtration at 0.1 µm and is stabilised by cooling to 18–20°C before the first wafer enters the batch. Bath life is usually 4–8 h under production conditions; after this period the peroxide concentration falls below 80% of its initial value, and the etch rate becomes non-uniform across the wafer.

For indium phosphide, a secondary H3PO4:HCl rinse is often required to remove insoluble indium chloride residues from the mesa sidewall before metal evaporation. The EL-grade acid for this application is analysed by ICP-MS with Au, Ag, and Cu each controlled at ≤10 ppb, because these metals can incorporate into the exposed channel and shift threshold voltage. The incoming acid also must be free of surfactant residues that alter wetting on narrow recess openings. The terminal features are pHEMT gate recess paths, ridge waveguides for photonic integrated circuits, and laser facet passivation structures. Published data for the exact sidewall roughness change at dilution ratios outside 1:1:15 to 1:1:30 is limited; foundries commonly qualify the specific ratio with focus-exposure matrix and scanning electron microscope metrology after each fresh bath preparation.

When EL-Grade Phosphoric Acid Enters Post-CMP Cleaning at Sub-5 g/L Loading

In post-chemical mechanical planarisation cleaning for copper damascene interconnects, dilute phosphoric acid is metered at 0.5–2 wt% into an organic acid buffer at pH 2.0–3.5 to remove silica abrasives and copper oxides after barrier CMP. The acid is dispensed through a single-wafer megasonic brush module at 25–35°C for 30–60 s, followed by ultrapure water rinsing. The phosphate anion complexes residual copper and reduces Cu line roughness from 0.8–1.2 nm RMS to below 0.5 nm RMS on 10 µm × 10 µm AFM scans. The additive also breaks electrostatic bonding between silica particles and the low-k surface, improving particle removal efficiency above 95% when the interfacial zeta potential is held between −10 mV and +10 mV. The upper loading limit is 2 wt%; above this value Cu dissolution exceeds 0.3 nm/min and line-edge pitting appears. At pH below 2.0, the formulation attacks SiOC low-k film and shifts dielectric constant by more than 0.1; above pH 3.5, particle removal efficiency drops below defect limits. Benzotriazole-based passivation is partially stripped, so cap deposition must follow within 2 h. The terminal wafer is copper/low-k logic or memory product at 28 nm and below design rules, with acid compliance tied to SEMI C36 and fab-specific defect density limits in the incoming-material quality agreement.

Photovoltaic Acid Texturing Baths and Surface Metal Budgets

Acid texturing of multicrystalline silicon wafers in high-throughput inline tools uses a ternary HF-HNO3-H2O mixture, and EL-grade phosphoric acid is blended at 1–3 vol% as a retarding additive that moderates the autocatalytic oxidation-dissolution reaction. The bath is operated at 6–12°C because the exothermic reaction raises local wafer temperature by 5–10°C; the H3PO4 addition reduces the formation of excess porous silicon and slows the etch rate from 3–5 µm/min to 1–3 µm/min. After texturing, the wafer reflectance is typically 22–25% at 600 nm when measured by a spectrophotometer with an integrating sphere. The acid additive also increases bath life by limiting the vapour pressure of nitrogen oxides and reducing consumption of nitric acid during a production shift of 8–12 h.

The metal impurity budget is the main reason for using EL-grade rather than technical-grade phosphoric acid in photovoltaic lines. Iron above 10 ppb, copper above 5 ppb, or nickel above 5 ppb in the texturing bath can deposit onto the wafer and degrade minority carrier lifetime below the threshold for high-efficiency PERC cells. The terminal product is a textured multicrystalline silicon wafer with saw damage removed and a homogeneous micro-reflective surface designed for subsequent diffusion and passivation. There is no universal photovoltaic fluid standard for this acid mixture; cell manufacturers typically reference SEMI C36 for incoming acid metal limits and add PV-specific transition-metal controls in their own qualification protocols. Published data for the exact reflectance shift at loadings below 1 vol% is limited, and process development relies on inline reflectometry rather than offline coupon tests.