In wafer-level copper pillar bumping on 300 mm silicon wafers, AZ-4620 Electronic/EL grade functions as a positive-tone electroplating mask for copper pillar heights from 20 µm to 80 µm. The resist is spin-coated to a dry film thickness of 12–18 µm using a coater track with dynamic dispense at 500 rpm for 3 s, followed by ramp to 2,500–3,500 rpm for 30 s. Softbake on a hot plate at 100 °C for 90 s drives residual solvent below the level that causes bubble formation during exposure. Exposure is performed with 365 nm i-line steppers or broadband aligners at a dose of 350–600 mJ/cm² for this thickness range. Puddle development in AZ 400K diluted 1:4 with deionized water at 20–23 °C for 120–180 s clears the exposed vias without excessive dark erosion; 2.38% TMAH is an alternative when tighter pH control is required. The patterned resist is hardbaked at 110 °C for 120 s before acid copper electroplating. Plating uses a high-acid copper sulfate bath containing 200 g/L CuSO₄·5H₂O and 50 g/L H₂SO₄, held at 25–28 °C and 2–4 A/dm², for 30–60 min depending on pillar height. The resist must survive this bath without lifting at the seed-layer interface; incoming adhesion is checked per ASTM D3359-23 on a control wafer and ionic cleanliness after stripping is verified by ion chromatography per IPC-TM-650 2.3.28. In production, adhesion failures are most commonly traced to insufficient dehydration bake when relative humidity exceeds 50% or to amine contamination in the coater environment. Stripping is performed in NMP or DMSO at 80 °C followed by an O₂/CF₄ plasma descum. The terminal product is a plated wafer with copper pillar bumps for flip-chip package assembly.

The ranges in the table are starting points for a 150–200 mm wafer track; exact values must be confirmed by profilometry and cross-section SEM on the specific coater, aligner, and developer bath because exhaust balance, chuck temperature, and developer age shift the process window by ±10–15%.

How Does Resist Sidewall Angle Influence Nickel Electroforming Uniformity in MEMS?

In MEMS electroforming, the sidewall angle of AZ-4620 molds directly controls local current-density distribution during nickel growth and the resulting metal sidewall taper. For a 20–25 µm mold, the resist is coated at 1,200–2,000 rpm, softbaked at 95 °C for 120 s, and exposed with collimated 365 nm UV at 800–1,200 mJ/cm² to reduce undercut. Development in 0.26 N TMAH with spray or puddle modes at 20 °C clears the template while limiting dark erosion. Cross-sectional SEM inspection is used because sidewall angle shifts with focus offset and dose; published data for every thickness configuration is limited, but optimized exposures typically maintain sidewall angles above 80° at 20 µm. After resist definition, nickel electroforming is done in a sulfamate bath containing 300 g/L nickel sulfamate and 40 g/L boric acid at pH 4.0, temperature 50 °C, and current density 1–5 A/dm². The resist mold must remain intact for 8–24 h, which requires the hardbake to be restricted to 110 °C for 120 s; higher temperatures cross-link the novolak matrix and make stripping difficult without damaging the nickel. A key process conflict is the trade-off between sidewall adhesion and strippability: hardbake improves resistance to the low-pH sulfamate bath but accelerates residue formation after stripping. Cleanroom operation is conducted under ISO 14644-1 Class 5 conditions, and resist adhesion before long plating cycles is confirmed with ASTM D3359-23 tape testing. The terminal products include micro gears, nozzle plates, and micro mold inserts where the resist sidewall defines the final metal sidewall taper.

Pattern plating of 12 µm blind-via structures on IC package substrates uses AZ-4620 as a thick cover resist on semi-additive process films. The starting substrate is an ABF lamination or BT laminate with a sputtered copper seed layer. The resist is dispensed dynamically and spun to 10–15 µm dry thickness to cover via lips and trace tops without starving the developing solution. Softbake at 95 °C for 90 s is followed by i-line exposure at 365 nm with a dose of 400–550 mJ/cm². Development uses AZ 400K diluted 1:4 with deionized water at 20 °C, applied as two 60 s puddles rather than one 120 s puddle to reduce scumming at the base of 12 µm vias. The resulting openings are enlarged by 1–2 µm per side through a subsequent oxygen descum at 50 W and 0.3 mbar. Acid copper pattern plating fills the vias and builds 12–18 µm trace thickness at 2 A/dm² and 25 °C using a bath with 200 g/L CuSO₄·5H₂O, 50 g/L H₂SO₄, and 50 ppm chloride ion. The resist is then stripped in NMP at 80 °C, and the seed layer is flash-etched. Fine-line patterns down to 12 µm line/space are produced with edge definition controlled by the resist foot rather than by etch undercut. Compliance of the finished package substrate is verified against IPC-6012 Class 3 requirements, and ionic contamination testing per IPC-TM-650 2.3.28 confirms that AZ-4620 residues do not exceed the required cleanliness limit. Terminal products are CSP and BGA package substrates for mobile and automotive processors.

When Thick Gold Pad Plating on GaN LED Wafers Demands a Sacrificial Mask That Survives Sulfite Gold Baths

For GaN/sapphire light-emitting diode wafers, AZ-4620 is applied as a sacrificial electroplating mask for Au pad thicknesses of 5–15 µm. Adhesion to the patterned dielectric on GaN requires a dehydration bake at 200 °C for 30 min and HMDS priming, because lateral electrolyte ingress at the dielectric/resist interface otherwise nucleates gold under the mask and creates shorting between adjacent pads. The resist is spin-coated to 8–10 µm and softbaked at 100 °C for 60 s. Exposure with 365 nm i-line at 250–400 mJ/cm² is followed by puddle development in 2.38% TMAH at 20 °C for 90–150 s. Gold plating is performed in a gold sulfite bath at pH 9.0–9.5 and 60 °C, with current density between 0.5 A/dm² and 1.0 A/dm²; the mask remains in contact with the bath for 15–30 min. The resist is not hardbaked above 110 °C because experience on production lines shows that higher hardbake temperatures slow stripping and leave carbonaceous residue on the gold surface after plasma clean. After plating, the resist is stripped in NMP at 80 °C, and the wafer is ashed in an O₂ plasma to remove residual novolak. Terminal gold pads must survive wire bonding and solder reflow; finished LED packages are evaluated under RoHS Directive 2011/65/EU for restricted substances in the final assembly. Cleanroom environment is maintained at ISO 14644-1 Class 6 or better. A known limitation is that strong ammonia-containing gold etchants can swell the novolak matrix; therefore wet gold etching is used only after mask stripping rather than as an in-process step with the resist present.

Thick copper redistribution layers on power semiconductor chips demand a resist that maintains sidewall integrity in high-throw acid copper baths for 40–60 min. AZ-4620 is coated to 18–22 µm on 200 mm or 150 mm wafers, softbaked at 100 °C for 120 s, and exposed with 365 nm i-line at 700–900 mJ/cm². Development in AZ 400K diluted 1:4 at 20 °C for 4–6 min clears the redistribution layer patterns; the long development time is required for 20 µm films but increases dark erosion if bath temperature is not controlled. After pattern inspection, a hardbake at 110 °C for 90 s is applied. Plating uses an acid copper bath containing 200 g/L CuSO₄·5H₂O, 50 g/L H₂SO₄, and 50 ppm chloride at 28 °C and 3 A/dm². The bath must not exceed 30 °C, because edge lift on passivation has been observed on production tools when heater overshoot is not controlled. Copper thickness after plating ranges from 20 µm to 40 µm, with the resist foot defining sidewall taper before seed etch. Stripping in NMP at 80 °C is followed by O₂ plasma ashing. Residual ionic cleanliness is checked per IPC-TM-650 2.3.28, and final wire bond pull strength is measured per MIL-STD-883 Method 2011.9. The terminal products are power MOSFET and IGBT chips with thick copper redistribution layers for high-current packages.

Interdigitated Electrode Fabrication on Alumina and Borosilicate Glass

Interdigitated electrode sensors on 96% alumina and borosilicate glass use AZ-4620 as an electroplating mask for Au or Pt fingers with line/space dimensions from 10 µm/10 µm to 50 µm/50 µm. The substrate is first coated with a Ti/Au seed layer by sputtering. The resist is spin-coated to 8–10 µm and softbaked at 100 °C for 60 s. Exposure at 365 nm with a dose of 300–450 mJ/cm² defines the finger apertures; development in 2.38% TMAH at 20 °C for 90–120 s clears the patterns. The mask is then hardbaked at 110 °C for 90 s. Gold plating is performed in a sulfite bath at pH 9.0–9.5 and 60 °C at 0.5–1.0 A/dm² to build 3–8 µm thick electrodes. After plating, the resist is stripped and the Ti/Au seed is removed by ion beam etching or wet chemical etching to isolate the fingers. Adhesion on ceramic and glass is confirmed by ASTM D3359-23 cross-cut testing, and particles are controlled under ISO 14644-1 Class 5 conditions. For platinum electroplating, the resist must resist longer bath exposure at elevated temperature; published data for AZ-4620 in platinum chloride systems is limited, and feasibility should be verified on each substrate because adhesion to glass is more sensitive to surface hydroxyl content than adhesion to alumina. The terminal products are impedance biosensors and chemiresistive sensor chips for water-quality and gas-detection modules.