| HS Code | 857369 |
| Material | Polyurethane resin with microporous cellular structure |
| Grade | Electronic/EL-grade for semiconductor and optoelectronic planarization |
| Porediameter | 0.5 to 5 micrometers |
| Porosity | 35 to 45 percent open-cell porosity |
| Hardness | 55 to 65 Shore D |
| Density | 0.45 to 0.60 grams per cubic centimeter |
| Compressibility | 1 to 3 percent at 5 psi |
| Tensilestrength | 5 to 15 MPa |
| Elongationatbreak | 50 to 100 percent |
| Thickness | 1.27 millimeters nominal |
| Surfaceroughness | Ra less than or equal to 0.5 micrometers after conditioning |
| Slurryretention | Rapid and uniform absorption of CMP slurry |
| Chemicalresistance | Stable across pH range of 3 to 11 |
| Defectivity | Low scratch and defect generation for EL-grade polishing |
As an accredited Microporous CMP Polishing Pad Electronic/EL Grade factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.
| Packing | Sealed in cleanroom-grade anti-static packaging, nitrogen-flushed to prevent contamination. Supplied as one electronic/EL grade pad per package. |
| Container Loading (20′ FCL) | Microporous CMP polishing pads, Electronic/EL grade, packed in cartons on pallets, securely loaded into 20′ FCL. |
| Shipping | Shipping: This CMP polishing pad is packaged in cleanroom-grade, moisture-barrier wrapping to preserve electronic-grade integrity. Shipped via temperature-controlled, impact-protected ground or express freight. Avoid direct sunlight, heavy pressure, and contamination during transit. Proper labeling prevents static damage and ensures safe, undamaged delivery. |
| Storage | Store in a clean, dry, temperature-controlled environment (15–30°C), away from direct sunlight, moisture, dust, and chemical fumes. Keep pads flat in original packaging to prevent warping, creasing, or surface contamination. Use clean nitrile gloves when handling. Maintain stable humidity below 60%. Follow manufacturer shelf-life guidelines for optimal performance. |
| Shelf Life | Typical shelf life is 12 months when stored sealed in original packaging under dry, ambient conditions. |
In 300 mm and 200 mm logic, NAND, and DRAM fabrication lines, shallow trench isolation and pre-metal dielectric planarization are executed on rotary CMP platforms—most commonly Applied Materials Mirra, Ebara F-REX300, or Tokyo Seimitsu tools—where the Electronic/EL grade microporous polyurethane pad is mounted on a precision-machined platen and conditioned in-situ by a diamond disc. The pad’s microporous cell structure governs slurry retention time, pad-to-wafer contact area, and removal product evacuation. Production-scale failure data from 300 mm fabs show that when the pad surface layer is not maintained by a 84–108 µm diamond conditioning disc at 0.45–0.75 kgf, or when ex-situ break-in with deionized water is shortened below 25 min, the PETEOS removal rate collapses from the stable range of 2,800–5,500 Å/min to below 2,000 Å/min within a single 25-wafer lot, while measured coefficient of friction shifts from 0.38–0.42 to 0.50–0.55. Industry compliance for this application references ASTM D2240-15 Shore D hardness of 52–58, ASTM D792-20 density of 0.65–0.85 g/cm³, ASTM D3574-17 compression set below 3.0% after 22 h at 70 °C, and cleanroom packaging compatible with ISO 14644-1:2015 Class 5 or stricter incoming-material protocols. The working oxide slurry is generated from a fumed silica or colloidal silica concentrate diluted with deionized water at a volumetric ratio of 1:1 to 1:3, producing 1.2–2.5 wt% abrasive solids in the final feed at pH 10.2–11.4 adjusted with aqueous KOH or NH4OH. In downstream production, the pad is fixtured with a pressure-sensitive adhesive, diamond-conditioned during wafer processing, and run at platen speed 55–90 rpm, carrier speed 52–87 rpm, downforce 2.5–5.0 psi (17.2–34.5 kPa), slurry flow 150–300 mL/min, and pad surface temperature 35–50 °C. Terminal finished product types include planarized shallow trench isolation and interlayer dielectric on logic SoCs, NAND flash dies, DRAM wafers, CMOS image sensors, and embedded memory devices before subsequent gate, contact, and interconnect lithography.
Copper dual-damascene interconnect planarization subjects the Electronic/EL grade microporous pad to an oxidizing, high-turbidity slurry environment that rapidly attacks the land area if pad asperity height is not restored. On production-scale 200 mm and 300 mm CMP systems, the pad is paired with point-of-use slurry blending units; a typical copper bulk working mixture is generated from a concentrated slurry containing 5–10 wt% colloidal silica or alumina by blending 1.0 L concentrate into 1.0–3.0 L deionized water, equivalent to a 1:1 to 1:3 volumetric dilution, followed by addition of 30 wt% hydrogen peroxide at 1.0–3.0 wt% of final working slurry and benzotriazole at 0.05–0.20 wt% with final pH 9.0–11.0; the oxidizer-to-concentrate addition ratio in point-of-use metering is normally 1:30 to 1:60 by volume when the concentrate contains 30 wt% H2O2. The pad in this operation must maintain Shore D 52–58 per ASTM D2240-15 and sufficient open microporosity to prevent slurry starvation at the die edge, but not so high that copper interfacial attack occurs by local peroxide pooling. A known production bottleneck is pad-to-pad thickness variation approaching 1.5–3.0% of nominal 1.27 mm; this creates low spots at the wafer edge and drives within-wafer removal non-uniformity above 5–8% one-sigma on 300 mm wafers after fewer than 300 electrical test wafers. Compliance references include REACH registration for polyurethane components, RoHS 2011/65/EU Annex II heavy-metal restrictions for exposed pad materials, ASTM D3574-17 for compression set, and ASTM D2240-15 for hardness in incoming inspection. Downstream production sequence includes copper bulk polishing at platen speed 30–60 rpm, carrier speed 28–57 rpm, downforce 1.5–4.0 psi (10.3–27.6 kPa), slurry flow 150–250 mL/min, then a low-pressure barrier removal step with acidic pH 2.5–4.5 colloidal silica slurry at downforce 1.0–2.0 psi. Terminal finished product types are microprocessors, SoCs, DRAM and NAND memory wafers, and copper interconnects at 7 nm and mature nodes.
High-density 2.5D and 3D packaging lines use through-silicon via copper overburden removal after electroplating, followed by seed and barrier removal and redistribution layer planarization on the same microporous pad stack. The copper reveal step demands a high stock removal rate—commonly 4–10 µm/min on via-field wafers—while maintaining scratch counts below 0.3/cm² and via dishing below 15–30 nm. Working slurry is blended from acidic copper bulk concentrate and deionized water at a volumetric ratio of 1:1 to 1:2, producing 0.8–2.0 wt% hydrogen peroxide, 0.5–1.5 wt% alumina or silica abrasive, and 0.05–0.15 wt% benzotriazole at pH 5.5–6.5; the subsequent barrier/seed removal formulation uses a 1:3 to 1:5 dilution of acidic colloidal silica concentrate at pH 2.0–3.5 and 0.25–0.75 wt% solids. The pad is characterized by ASTM D2240-15 Shore D 52–56, ASTM D792-20 density 0.68–0.78 g/cm³, and ASTM D3574-17 compression set below 2.5%; advanced packaging incoming inspection also records groove depth 300–500 µm and pad thickness total variation ≤1.5% before mounting. Conditioning is conducted with a 70–84 µm diamond disc at 0.35–0.50 kgf while pad temperature is held at 28–40 °C; the process runs at platen speed 40–70 rpm, carrier speed 38–66 rpm, downforce 1.0–2.5 psi (6.9–17.2 kPa), and slurry flow 100–200 mL/min. Terminal finished product types include high-bandwidth memory silicon interposers, GPU/CPU 2.5D packages, wafer-level fan-out redistribution layers, and backside-illuminated CMOS stacked-sensor wafers.
Prime silicon wafer suppliers operating final single-side polishing on 300 mm substrates shift to a soft microporous polyurethane pad whose compressibility under ASTM D3574-17 is held between 1.0% and 2.8%, because pad-induced nanotopography and edge roll-off are the dominant rejection causes for epitaxy and silicon-on-insulator starting wafers. In this ultralow-defect application the working slurry is generated by diluting a concentrated aqueous colloidal silica sol with deionized water at a ratio between 1:20 and 1:50 by volume, yielding 0.03–0.10 wt% silica solids at pH 10.0–11.0; this extremely low solids loading is intentionally below semiconductor CMP slurry norms because final wafer polishing removes only 50–200 nm of silicon and must not create pits, haze, or light-point defects. Downstream production tools typically employ single-sided polishers with sub-aperture pad conditioning and wafer templates that hold flatness deviation below 10 µm; process parameters are downforce 0.5–1.2 psi (3.4–8.3 kPa), platen speed 20–50 rpm, slurry flow 50–150 mL/min per wafer, and station-to-station polish time 60–120 s. Compliance for the polished substrate references SEMI M1 substrate dimensional and flatness requirements and ISO 14644-1:2015 cleanroom particle control. Terminal finished product types include epitaxial-ready p/p− and n/n− substrates, silicon-on-insulator base wafers, and thermally oxidized starting wafers; the wafer surface after this operation is routinely qualified by atomic force microscopy at RMS roughness ≤0.15 nm and light-point defect counts below 50 defects at ≥0.12 µm per 300 mm wafer.
Wide-bandgap semiconductor production is distinct from silicon CMP because the removal mechanism shifts to mechanically dominated surface amorphization and abrasive ploughing in the Si-face of 4H-SiC or the Ga-face of GaN, and the microporous pad must absorb sharp abrasive loading without catastrophic land-area collapse. A production-scale high-torque CMP tool—commonly equipped with platen drives rated for 15–22 kW and rigid steel platens—is used for 150 mm or 200 mm SiC wafers; the working slurry is formulated from polycrystalline diamond or α-alumina concentrate and deionized water at a volumetric ratio of 1:0 to 1:3, resulting in 0.2–2.0 wt% diamond or 1.0–5.0 wt% α-alumina abrasive at pH 2.0–4.0 for acid chemistries or 9.5–11.0 for alkaline alumina slurries. The pad is graded by ASTM D2240-15 Shore D 45–55 for hard-substrate CMP and by ASTM D792-20 density 0.60–0.80 g/cm³; the principal field failure is non-uniform pad wear, with groove depth loss of 10–30 µm per 100 wafers when a 70–90 µm diamond conditioner is run at 0.50–0.75 kgf. Material removal rates on Si-face 4H-SiC are commonly 0.1–2.0 µm/hr depending on abrasive type and pH. Process parameters include downforce 3.5–7.0 psi (24.1–48.3 kPa), platen speed 50–110 rpm, slurry flow 50–150 mL/min, and pad surface temperature 30–45 °C. Compliance references ISO 14644-1:2015 for wafer-surface cleanroom protocols and ASTM D2240-15 for pad hardness batch-release testing. Terminal finished product types include SiC MOSFET power device wafers, GaN-on-SiC RF wafers, sapphire LED carriers, and 5G RF front-end substrates.
Tungsten contact and via plug planarization in DRAM, 3D NAND, and logic front-end-of-line places the Electronic/EL grade microporous pad in an acidic oxidizer environment where open-cell moisture ingress can cause pad delamination or groove-edge roughening. Tungsten CMP slurries are commonly prepared by diluting an alumina or silica concentrate with deionized water at a volumetric ratio of 1:1 to 1:2, yielding 2.0–5.0 wt% abrasive solids at pH 2.0–3.5 with ferric nitrate at 0.5–1.5 wt% or hydrogen peroxide at 1.0–3.0 wt% as oxidizer; the low pH and oxidizer load demand a pad with Shore D 52–58 per ASTM D2240-15 and compression set below 2.5% per ASTM D3574-17. Production lines track platen torque endpoint rather than fixed wafer count because pad aging under ferric ions is nonlinear; tungsten removal rate is commonly held at 3,000–6,000 Å/min with downforce 2.0–5.0 psi (13.8–34.5 kPa), platen speed 40–80 rpm, slurry flow 80–180 mL/min, and pad surface temperature 30–45 °C. Published industrial data for the exact pore-size threshold that controls tungsten plug defectivity is limited; incoming-tool qualification therefore uses torque endpoint tracking and optical wafer inspection rather than a single pad specification. Compliance for pad cleaning and packaging references ISO 14644-1:2015 Class 5. Terminal finished product types include DRAM word-line and bit-line contact arrays, 3D NAND tungsten via chains, and logic front-end contact plugs.
| Process parameter | Oxide ILD/STI | Cu bulk/damascene | TSV copper reveal / RDL | Prime Si final polish | SiC/GaN substrate CMP | W contact / via plug |
|---|---|---|---|---|---|---|
| Pad Shore D per ASTM D2240-15 | 52–58 | 52–58 | 52–56 | soft grade, compression set 1.0–2.8% | 45–55 | 52–58 |
| Density per ASTM D792-20 | 0.65–0.85 g/cm³ | 0.65–0.85 g/cm³ | 0.68–0.78 g/cm³ | 0.60–0.80 g/cm³ | 0.60–0.80 g/cm³ | 0.65–0.85 g/cm³ |
| Downforce | 2.5–5.0 psi | 1.5–4.0 psi | 1.0–2.5 psi | 0.5–1.2 psi | 3.5–7.0 psi | 2.0–5.0 psi |
| Platen speed | 55–90 rpm | 30–60 rpm | 40–70 rpm | 20–50 rpm | 50–110 rpm | 40–80 rpm |
| Slurry flow | 150–300 mL/min | 150–250 mL/min | 100–200 mL/min | 50–150 mL/min | 50–150 mL/min | 80–180 mL/min |
| Working slurry dilution ratio | 1:1 to 1:3 | 1:1 to 1:3 plus H2O2 1:30 to 1:60 | 1:1 to 1:2; barrier 1:3 to 1:5 | 1:20 to 1:50 | 1:0 to 1:3 | 1:1 to 1:2 |
| Representative removal rate target | 2,800–5,500 Å/min | 4,000–7,000 Å/min bulk; barrier 300–800 Å/min | 4–10 µm/min Cu reveal | 50–200 nm Si removal per process | 0.1–2.0 µm/hr | 3,000–6,000 Å/min |
| Standard / regulation | Test or inspection parameter | Application context |
|---|---|---|
| ASTM D2240-15 | Shore D hardness | Incoming pad lot release for all CMP pad grades |
| ASTM D792-20 | Specific gravity / density | Microporous polyurethane matrix consistency |
| ASTM D3574-17 | Compression set and compressibility | Pad deformation under platen load and conditioner pressure |
| ISO 14644-1:2015 | Cleanroom particle classification | Pad cleaning and packaging for semiconductor fabs |
| RoHS 2011/65/EU | Heavy-metal restrictions | Exposed pad materials in electronic-grade handling |
| SEMI M1 | Polished silicon wafer flatness and surface requirements | Prime silicon final polish downstream quality gate |
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Microporous CMP polishing pads supplied under the Electronic/EL designation are closed-cell polyurethane foam planarization substrates intended for oxide interlevel dielectric, shallow trench isolation, and selected first-step copper polishing operations on 200 mm and 300 mm rotary polishing platforms. The pad contains a continuous polyurethane matrix in which discrete spherical microvoids are introduced during casting and cure. The resulting surface controls slurry transport through sequential compression and recovery as the wafer passes across the platen. Unlike open-cell or nonwoven pads used in rough stock removal, the Electronic/EL grade provides a narrower pore-size distribution and lower extractable contamination, which makes it suitable for device nodes where pad-derived defects and trace metal contamination are process-limiting.
Physical characterisation for each production lot follows ASTM D2240-15 for durometer hardness, ISO 1183-1:2019 for bulk density, and ASTM D3574-17 for compression set and recovery. Representative qualification data place Shore D hardness between 52 and 58, density between 0.62 g/cm³ and 0.78 g/cm³, and compression set below 15 % after 22 h at 70 °C. Pore-size distribution is measured by mercury intrusion porosimetry according to ISO 15901-1:2016; the D50 typically falls between 10 μm and 25 μm, and the D10–D90 span is held below 18 μm for Electronic/EL lots. This span is narrower than that of general-purpose microporous pads, which may show D10–D90 spans above 35 μm on the same test method.
Total pore volume alone does not determine the slurry film thickness between wafer and pad. The pad stores slurry in surface voids, releases it under wafer compression, and then recovers to refill from groove channels. If the void network is too open, slurry residence time increases and abrasive particles settle or agglomerate along groove edges; if the void network is too closed, the wafer experiences local hydrodynamic starvation and the removal rate becomes sensitive to minor variations in downforce. The Electronic/EL grade controls the ratio of closed-cell to open-cell volume during curing, and lot release includes cross-sectional image analysis of pore fraction at five radial positions. The acceptance range for pore fraction is typically 35 % to 45 % by area, with a radial variation below 3 percentage points.
Slurry viscosity and pad surface energy further influence how the microvoids fill and drain. Fumed silica slurries with solid loadings of 10–12 wt% at pH 10.5–11.0 exhibit shear-thinning behaviour with low-shear viscosity between 5 mPa·s and 20 mPa·s when measured by a cone-and-plate rheometer at 25 °C. The Electronic/EL grade is characterised by a water contact angle below 80° after break-in, which promotes wetting and reduces air bubble entrapment at the wafer edge. Surface energy is verified by sessile drop contact angle on production lots using deionized water per ASTM D7490-13. If contact angle exceeds 85°, the lot is recleaned or rejected because poor wetting increases the probability of slurry film rupture.
On 300 mm multi-platen systems operated at 2.0–5.0 psi downforce and platen speeds of 60–90 rpm, this controlled void structure stabilises the Preston coefficient across pad break-in. The first 10–20 wafers after pad installation exhibit transient removal-rate drift as the surface skin is removed and diamond conditioning establishes steady-state microtexture. Conditioner downforce is maintained between 0.5 lbf and 2.0 lbf; above 2.0 lbf, pad life decreases and pad particle shedding increases without a proportional removal-rate benefit. Removal-rate variation across a 25-wafer qualification lot on blanket oxide monitors is typically below 6 % when the pad is conditioned continuously and slurry flow is held at 150–300 mL/min. Below 150 mL/min on a 300 mm platen, starvation-induced non-uniformity increases sharply; above 300 mL/min, the additional slurry volume does not improve removal stability and increases chemical consumption.
The microporous surface is compatible with aqueous fumed silica and ceria slurries within pH 2–11. Outside this range, hydrolysis of urethane linkages accelerates and the surface softens, causing pore collapse and pad glazing. The pad should not be allowed to dry after slurry contact because residual abrasive crystallisation inside microvoids creates hard inclusions that raise microscratch density on subsequent wafers. Rinse with deionized water and maintain platen rotation at low speed during idle periods.
Grooved formats of the Electronic/EL grade use concentric, logarithmic, and cross-hatch patterns. Groove depth is selected from 0.4 mm to 0.8 mm and groove width from 0.4 mm to 0.6 mm; the specific sub-designation is tied to the target removal profile on the customer’s polishing tool. Grooves are not passive drainage channels: their intersection density changes the slurry residence time, the pad surface temperature, and the radial removal profile. On rotary tools with in-situ conditioning, a cross-hatch pattern with 0.6 mm pitch and 0.6 mm depth typically produces lower edge-fast non-uniformity in blanket oxide CMP than a concentric groove pattern at the same pitch, although the difference is tool-specific and must be verified on the target platform.
After break-in, pad surface roughness measured by stylus profilometry is typically Ra 4–8 μm. If Ra falls below 3 μm, the surface has glazed and removal rate decays; if Ra exceeds 12 μm, pad-derived particle shedding increases and defect counts on unpatterned monitors rise. This process window is maintained by closed-loop conditioner control. On production-scale 300 mm CMP tools with integrated endpoint detection, pad replacement is generally triggered by removal-rate loss greater than 15 % relative to the stable post-break-in baseline, or by wafer-level non-uniformity above 8 % on blanket oxide wafers. Fixed wafer-count replacement is not recommended because slurry chemistry, downforce, and conditioner condition shift pad degradation rate.
The microporous structure reduces the break-in transient relative to solid cast polyurethane pads because the closed-cell walls offer lower resistance to diamond conditioning. However, if the pad is installed with an aggressive conditioner disc above 2.0 lbf during the first 10 wafers, excessive cutting opens surface voids and increases slurry retention, which can produce a non-recoverable rise in defect density. The recommended start-up sequence is to run conditioner break-in on a dummy wafer for 10–15 min at 1.0 lbf before processing product wafers.
The Electronic/EL grade differs from standard bulk-foam pads in three measurable respects. First, the pore-size distribution is narrower. Mercury porosimetry data show a D10–D90 span below 18 μm for the Electronic/EL grade, whereas general-purpose microporous pads can span 5–40 μm or more. Oversized voids act as slurry-starvation defects on highly patterned wafers; narrowing the span reduces the tail of the distribution that produces localised dry spots at the wafer edge. Second, extractable contamination is controlled. Certificate of conformance reports acid-digested element concentrations for iron, copper, sodium, potassium, calcium, and magnesium by ICP-MS, with reporting limits typically below 1.0 mg/kg for each element. Standard industrial foam pads may contain higher iron and calcium residues that transfer to the wafer during metal CMP. Third, crosslink density is higher, which reduces plastic flow and glaze formation during ceria-based shallow trench isolation polishing at elevated platen temperatures. This difference is measurable as a lower change in storage modulus after 24 h of continuous polishing in a ceria slurry at 50–60 °C surface temperature.
The product is not a drop-in replacement for every pad stack. Because the Electronic/EL grade has lower bulk density than solid polyurethane pads, the sub-pad compression behaviour exerts a stronger effect on removal profile. A sub-pad with compressibility below 2 % under 3 psi load can suppress the conformality benefit of the microporous top pad and produce high edge removal on dense line arrays. A sub-pad with compressibility above 6 % can produce excessive center-slow profiles and transistor gate height loss. The manufacturer recommends sub-pad compression testing per ASTM D3574-17 and wafer-profile mapping on a 25-wafer qualification lot before changing sub-pad hardness.
In copper first-step polishing with abrasive-free or low-abrasive slurries containing benzotriazole and hydrogen peroxide, the Electronic/EL grade performs best when the incoming copper step height is below 200 nm. Above this topography, a harder solid polyurethane pad or a stacked pad configuration may be required to maintain within-die planarization efficiency. For oxide CMP, the pad can be used directly on standard hard or soft sub-pads, but the removal profile must be re-qualified after any sub-pad vendor change because sub-pad thickness tolerance and surface roughness affect the effective pad stiffness.
Each Electronic/EL grade lot is shipped with a qualification report that includes the compliance matrix shown below. The values are representative of recent production lots and are not universal specification limits; customer-specific limits may supersede these values.
| Parameter | Test method or regulation | Representative acceptance range/status |
|---|---|---|
| Hardness | ASTM D2240-15 | 52–58 Shore D |
| Bulk density | ISO 1183-1:2019 | 0.62–0.78 g/cm³ |
| Compression set | ASTM D3574-17 | ≤15 % after 22 h at 70 °C |
| Pore-size D50 | ISO 15901-1:2016 | 10–25 μm |
| Restricted substances | RoHS Directive 2011/65/EU | Below maximum concentration values |
| SVHC declaration | REACH Regulation (EC) No 1907/2006 | Supplied per Article 33 |
Storage of unopened pads should be maintained at 15–25 °C and 30–70 % RH. Direct UV exposure and ozone concentrations above 0.05 ppm accelerate oxidative degradation of the polyurethane surface and increase surface hardness variability. Pads should be acclimated in the CMP bay for 24 h before installation to avoid dimensional shift from thermal expansion. Spent pads must be disposed under applicable semiconductor waste regulations; the closed-cell polyurethane matrix is not classified as hazardous under Regulation (EC) No 1272/2008, but slurry residues may alter disposal classification. The Electronic/EL grade is not recommended for polishing substrates other than silicon wafers, such as gallium arsenide or silicon carbide, unless a dedicated qualification has been completed because slurry chemistry and pad wear rates differ substantially.
