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Low-K Dielectric Polishing Slurry Electronic/EL Grade

    • Product Name: Low-K Dielectric Polishing Slurry Electronic/EL Grade
    • Factroy Site: Yudu County, Ganzhou, Jiangxi, China
    • Price Inquiry: admin@ascent-chem.com
    • Manufacturer: Ascent Petrochem Holdings Co., Limited
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    Specifications
    HS Code 754084
    Product Type Low-K Dielectric Polishing Slurry Electronic/EL Grade
    Abrasive Type Colloidal silica based
    Appearance Milky white liquid
    Ph 9.0 - 10.5
    Viscosity 2.0 - 5.0 mPa·s at 25°C
    Solids Content 10.0 - 15.0 wt%
    Average Particle Size 30 - 60 nm
    Density 1.02 - 1.08 g/cm3 at 25°C
    Metal Impurities Fe, Cu, Na, K, Ca, Mg each ≤ 1 ppb
    Filtration Rating ≤ 0.1 μm
    Removal Rate Selectivity Low-k to SiO2 selectivity ≥ 20:1
    Storage Temperature 5 - 35°C
    Shelf Life 6 months from date of manufacture

    As an accredited Low-K Dielectric Polishing Slurry Electronic/EL Grade factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.

    Packing & Storage
    Packing Sealed HDPE packaging protects purity; available in 1-gallon quantities. Low-K Dielectric Polishing Slurry, Electronic/EL grade, ensures contamination-free precision use.
    Container Loading (20′ FCL) 20' FCL: drummed, palletized EL-grade slurry; secure bracing, temperature-controlled, clean, moisture-proof container for electronic chemical safety.
    Shipping This chemical is shipped in sealed, certified HDPE drums or IBCs to prevent leakage and contamination. Transport is via ground or air freight under ambient conditions. Ensure containers remain upright, protected from freezing, and labeled per SDS. Proper PPE is required during handling and unloading.
    Storage Store in a clean, cool, dry, well-ventilated area in the original tightly sealed container. Protect from direct sunlight, freezing, and temperatures above 30°C (86°F). Keep away from incompatible materials such as strong acids or oxidizers. Avoid prolonged agitation; mix gently before use. Ensure container remains sealed to prevent evaporation, contamination, or particle settling.
    Shelf Life Shelf life is typically 6 months when stored unopened in original containers at recommended temperatures, with periodic agitation to prevent settling.
    Application of Low-K Dielectric Polishing Slurry Electronic/EL Grade

    Dual-Damascene SiCOH Planarization Before Via Patterning

    In advanced logic back-end-of-line integration at the 7 nm, 5 nm, and 3 nm nodes, the low-k dielectric polishing slurry is inserted after flowable chemical vapour deposition of an organosilicate film and its subsequent ultraviolet-cure step that removes porogen and stabilizes dielectric constant. The material is a colloidal silica system with mean particle size in the 60 nm90 nm range by ISO 22412:2017 dynamic light scattering, a pH of 9.510.5 by ISO 10523, and solids loading from 0.5 wt% to 2.0 wt%. The electronic/EL-grade classification under SEMI C1 imposes tighter cation and anion ceilings than general industrial silica dispersions. On 300 mm polishers such as the Applied Materials Reflexion LK or Ebara F-REX300, the slurry is point-of-use filtered and delivered at 120 mL/min200 mL/min to a polyurethane IC1010 pad with a Suba IV subpad and in-situ diamond conditioning. Carrier membrane pressure zones are set to maintain 0.8 psi1.2 psi average downforce, while platen and carrier speeds are held at 87 rpm and 83 rpm respectively. The process removes local step height from spin-on or flowable low-k deposition so that the subsequent via lithography operates inside the ±50 nm depth-of-focus window for immersion scanners. Endpoint is based on optical reflectance; the final dielectric thickness after polish is controlled within ±50 Å across the wafer. The resulting 300 mm wafer carries a carbon-doped oxide surface with root-mean-square roughness below 0.5 nm on a 5 µm × 5 µm atomic force microscopy scan, which is a prerequisite for low-defect trench etching. The electronic/EL-grade supply acceptance protocol includes large particle count below 100 counts/mL at ≥0.2 µm by an ISO 21501-2-calibrated optical particle counter, trace metal content below 10 ppb per element by ASTM D5673 inductively coupled plasma mass spectrometry, and chloride below 100 ppb by ASTM D4327 ion chromatography. Slurry drums are stored at 10°C25°C; freeze-thaw cycles are not permitted because irreversible aggregation occurs. A documented operational boundary is that porous SiCOH with modulus below 10 GPa must not be polished at downforce above 1.5 psi, because cohesive failure and permanent k-value increase occur before the optical endpoint can respond.

    Why Porous SiCOH Films Demand Sub-1.0 psi Downforce During Barrier Clearance

    Barrier clearance after copper bulk CMP creates the most direct contact between slurry chemistry and mechanically fragile porous SiCOH. The slurry is introduced after copper bulk removal to clear residual TaN barrier while minimizing dielectric loss. The main process conflict is that barrier removal rate falls as downforce is reduced, but porous low-k films with porosity above 20% and elastic modulus below 8 GPa begin to exhibit surface collapse and carbon depletion if local shear exceeds the fracture threshold. Production recipes therefore operate at 0.6 psi1.0 psi average downforce on a soft polyurethane pad with compressibility between 2% and 4%, using a 1:2 to 1:3 dilution of the electronic-grade slurry in ultrapure water. The diluted slurry is characterized by a viscosity below 2.0 mPa·s at 1,000 s⁻¹ shear rate by ISO 3219 cone-and-plate rheometry, because higher viscosity retards pad-wafer interface fluid transport and produces a thicker hydrodynamic film that reduces barrier removal at the same downforce. The chemistry is formulated without peroxide so that copper corrosion is suppressed and the carbon-doping level of the dielectric is not oxidized. Selectivity engineering is achieved through polymeric passivation agents that adsorb onto the low-k surface while the abrasive particles remove oxidized barrier material; published selectivity data for all device-specific TaN/low-k combinations is limited, so inline fabs run design-of-experiment matrices on patterned short-loop wafers before release. Motor current endpoint and optical emission are used jointly to stop on the low-k film with final dielectric loss below 50 Å on the array. Post-CMP cleaning uses megasonic energy at 925 kHz in dilute citric acid at pH 6.57.5, which prevents redeposition of silica particles on the hydrophobic porous surface. The end product is a Cu/low-k wafer with copper recess below 5 nm, residual TaN below the detection limit of x-ray photoelectron spectroscopy, and surface roughness below 0.8 nm root-mean-square. A critical operational boundary is pad conditioning: aggressive diamond conditioning increases pad micro-texture and shear stress at the wafer edge, while insufficient conditioning causes the slurry film to thin and produces non-uniform barrier removal.

    When TaN Barrier Polish Stops Directly on k 2.55 CDO Dielectric

    For radio-frequency integrated circuit fabrication on high-resistivity silicon substrates, copper damascene structures with k ≈ 2.55 carbon-doped oxide require a final barrier polish that stops directly on the dielectric without introducing mobile ion contamination. This application differs from conventional logic BEOL because the dielectric loss tangent of the CDO directly affects inductor Q factor and capacitor linearity in the 2 GHz28 GHz range. Inductor Q factor is extracted from vector network analyser S-parameter measurements using a Short-Open-Load-Through calibration substrate. The slurry is specified with chloride below 50 ppb, sulfate below 50 ppb, and nitrate below 50 ppb by ASTM D4327 ion chromatography, because halide residues accelerate copper oxidation after the wafer leaves the cleaner. The formulation is oxidizer-free and contains a low-molecular-weight alcohol to maintain contact angle below 20° on the CDO surface without swelling the film. A typical process on an Ebara F-REX300 uses 0.8 psi downforce, 70 rpm platen speed, 75 rpm carrier speed, slurry flow of 150 mL/min, and a 1:2 dilution ratio. Endpoint is controlled by optical reflection with a fixed over-polish of 10%15% to account for within-wafer variation. The resulting passive device structure includes copper inductors and metal-insulator-metal capacitors with surface roughness below 0.4 nm root-mean-square on 1 µm × 1 µm atomic force microscopy scans. The primary operational boundary is pH: below pH 6.5, the slurry can etch the CDO through hydrolytic attack on siloxane bonds, and above pH 10.5, the abrasive colloid becomes shear-thickening under high platen speed. Therefore point-of-use pH is maintained at 9.09.5 and verified every shift with ISO 10523 calibration buffers.

    Advanced Memory Periphery and Carbon-Doped Oxide Polish Control

    DRAM periphery integration at 1x-nm nodes uses carbon-doped oxide between bitline and storage-node levels to reduce parasitic capacitance in the array periphery. The slurry polishes the CDO film after deposition and stops on an underlying silicon nitride polish-stop layer, so selectivity to silicon nitride must be kept at or above 10:1 under production downforce. The polish platform is a 300 mm rotary or orbital CMP tool equipped with a 49-point polar ellipsometry metrology cassette and 3 mm edge exclusion. A representative process uses a 1:1 to 1:4 point-of-use dilution, downforce of 1.0 psi, platen speed 80 rpm, carrier speed 80 rpm, and a slurry flow rate of 180 mL/min. Silicon nitride loss is measured after stripping the CDO in a dilute HF solution, and the selectivity window is maintained by adjusting the slurry’s quaternary ammonium compound concentration within 0.1 wt%0.3 wt%. Within-wafer non-uniformity is held below 3% one-sigma, while dishing in 50%-density line arrays is kept below 150 Å to preserve subsequent self-aligned contact overlay. The end product is a DRAM wafer with planar CDO thickness remaining on array and periphery that meets the etch depth budget of the subsequent self-aligned contact process. The main operational boundary is pattern density: arrays with density variation above 30% from center to edge cause variable removal rate because the local slurry residence time changes, so the tool recipe uses multi-zone carrier pressure compensation to flatten edge fast polish. Published data for this specific application configuration is limited, so individual fabs verify selectivity and defect count using production representative short-loop wafers before committing batch lots.

    Electronic-grade low-k dielectric CMP slurry acceptance and test method matrix
    ParameterTest method/standardRepresentative supplier specification envelope
    Mean particle sizeISO 22412:2017 dynamic light scattering6090 nm
    Large particle count at ≥0.2 µmISO 21501-2 optical particle counter100 counts/mL
    Trace metal cationsASTM D5673 ICP-MS10 ppb per element
    pHISO 105239.510.5
    Zeta potentialISO 13099-1:201230 to −50 mV

    Short-loop CMP qualification in an advanced-node ramp consumes the slurry on patterned test wafers before device production begins. A 300 mm polisher is loaded with oxide, silicon nitride, and copper patterned short-loop masks having linewidths from 0.04 µm to 0.5 µm and pitches from 0.08 µm to 1.0 µm. The slurry is run at downforce splits of 0.6 psi, 0.8 psi, and 1.0 psi on an IC1010 pad with diamond conditioning at 6 lbf to 8 lbf conditioning force and in-situ pad break-in. Removal rate, within-wafer non-uniformity, and edge exclusion are extracted from 49-point polar maps; dishing and erosion are quantified by atomic force microscopy on dense and isolated structures. The test lot protocol includes particle count and zeta potential stability over 14 days of recirculation: mean particle size drift of less than 5 nm and large particle count below 150 counts/mL are regarded as process-capable. This application does not yield a sellable die; it produces the process-window data that determines whether the slurry can be released for a specific Cu/low-k dielectric stack. The central operational boundary is that short-loop wafers made from blanket films overestimate removal rate and underestimate pattern-dependent erosion, so the results are never directly transferred to device lots without a patterned wafer confirmation run.

    At point-of-use in sub-7 nm fab chemical distribution networks, inline blending of electronic-grade low-k dielectric polishing slurry with ultrapure water determines final polish performance more than the as-delivered lot. The slurry is supplied in 200 L polyethylene drums or 1,000 L intermediate bulk containers and is transferred through low-shear diaphragm pumps into PFA distribution lines. Ultrapure water at 18.2 MΩ·cm resistivity and total organic carbon below 5 ppb is blended at a mass-flow-controlled ratio, typically 1:1 to 1:4, immediately upstream of the 0.2 µm point-of-use filter. The filter membrane is selected for low zeta potential interaction with the colloidal silica particles; otherwise filter-induced agglomeration can raise large particle counts at the platen. Recirculation velocity is kept between 0.5 m/s and 1.0 m/s to prevent settling without subjecting the slurry to shear-induced aggregation. Final blended slurry is monitored for pH by in-line pH probes calibrated to ISO 10523, and for particle count by an ISO 21501-2 optical particle counter. Diluted slurry is not stored longer than 24 hours because the colloidal system loses electrostatic stabilization after dilution. The end product is a consistent platen-level dispersion with large particle count below 50 counts/mL at ≥0.2 µm, which is necessary for defect densities below 50 counts per wafer on dark-field laser scanning inspection calibrated with polystyrene latex spheres. The principal operational incompatibility is with amine-based post-CMP cleaners introduced upstream; even trace amine carryback into the slurry return line can destabilize the zeta potential and produce filter blinding.

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    Certification & Compliance
    More Introduction

    Model LK-EL-310 is used in this document as the product identifier for the electronic/EL-grade low-k dielectric polishing slurry employed in chemical mechanical planarization of carbon-doped oxide and organosilicate glass interlayer dielectrics in copper/low-k back-end-of-line integration. The formulation is a colloidal silica-based aqueous dispersion with a nominal pH of 10.0–11.5, a z-average particle diameter of 20–50 nm determined by dynamic light scattering per ISO 22412:2017, and a polydispersity index below 0.10. The product is supplied for rotary CMP platforms with polyurethane pad stacks. On 300 mm production tools, representative starting parameters are a downforce of 1.0–3.0 psi (6.9–20.7 kPa), platen speed of 30–70 rpm, and slurry flow of 100–300 mL/min. The EL-grade designation does not signal a higher absolute removal rate; it refers to reduced metallic contamination, controlled large particle counts, and greater batch-to-batch consistency relative to standard semiconductor-grade dielectric polishing slurries.

    Which Physical and Chemical Specifications Govern the EL-Grade Slurry?

    For porous low-k films with k ≤ 2.4, mobile ion contamination is a dominant reliability risk because sodium and potassium migration under bias-temperature stress shifts flatband voltage and can degrade time-dependent dielectric breakdown. The EL grade is therefore controlled to keep sodium and potassium below 100 ppb each by inductively coupled plasma mass spectrometry after acid digestion, and chloride below 200 ppb by suppressed-conductivity ion chromatography per ASTM D4327-17. Cation analysis is performed by ion chromatography per ASTM D6919-17. Large particle counts for particles ≥ 0.5 µm are maintained below 50 particles/mL using light-obscuration counting calibrated against ISO 21501-2:2019. The viscosity at 25 °C is 1.4–2.8 mPa·s per ASTM D2196-20, and the zeta potential is more negative than -20 mV at the supplied pH. These values represent the qualification framework for the LK-EL-310 product; they are not a certified certificate of analysis.

    ParameterTest method / instrumentTypical EL-grade control window
    pHASTM E70-19 glass electrode10.0–11.5
    Z-average particle diameterISO 22412:2017 dynamic light scattering20–50 nm
    Polydispersity indexISO 22412:2017< 0.10
    Zeta potentialISO 13099-1:2012more negative than -20 mV
    Viscosity at 25 °CASTM D2196-20 Brookfield LV1.4–2.8 mPa·s
    Large particle count ≥ 0.5 µmISO 21501-2:2019 light obscuration< 50 particles/mL
    Sodium and potassiumASTM D6919-17 ion chromatography< 100 ppb each
    ChlorideASTM D4327-17 ion chromatography< 200 ppb
    Total trace metalsEPA 6020B inductively coupled plasma mass spectrometry< 1 ppm total
    Blanket SiCOH removal rateSpectroscopic ellipsometry on k ≈ 2.4 blanket film40–120 nm/min; process-dependent

    Published data for this specific configuration is limited; the removal-rate row in the table reflects a representative process window on blanket films, not a universal product specification. Lot release tests for the electronic/EL grade normally cover pH, z-average particle size, large particle count, viscosity, sodium, potassium, chloride, and total trace metals. Removal rate and selectivity are validated on the end-user dielectric stack because film composition, porosity, cap material, and post-etch residue vary across integration schemes.

    Compared with conventional silicon oxide CMP slurries that typically contain 10–20 wt% fumed silica, the EL-grade product is formulated with a lower colloidal silica loading of 1–5 wt%. The difference is measurable by post-polish atomic force microscopy on a 2 × 2 µm scan area, where blanket carbon-doped oxide after buff typically records a root-mean-square roughness below 0.5 nm. Conventional oxide slurries on the same porous low-k film can produce higher scratch counts and embedded abrasive residues because their higher solids content and abrasive morphology are optimized for dense oxide removal rather than mechanically fragile low-k films. Compared with barrier slurries designed for copper, tantalum, and tantalum nitride removal, the EL-grade slurry does not contain aggressive copper complexing agents. Copper corrosion during dielectric buff is therefore reduced; on copper sheet coupons, the static etch rate at 25 °C is typically below 5 nm/min when measured by four-point probe sheet resistance change. The product is not intended for bulk copper removal or as a single-step copper/tantalum slurry.

    In manufacturing, the electronic/EL grade is produced with dedicated passivated stainless steel or high-density polyethylene vessels rinsed with ultrapure water to avoid metallic contamination. Transfer lines use fluoropolymer or polypropylene components. This equipment set is selected because standard stainless steel piping with elastomeric seals can contribute iron, chromium, and sodium ions that exceed the 100 ppb alkali limit and alter large particle count through corrosion. These production-scale controls are part of the EL-grade difference from research-grade slurries that may be manufactured in non-dedicated containers.

    On a 300 mm high-volume CMP line equipped with a polyurethane IC1000 pad and a Suba IV subpad, the EL-grade slurry is applied as a direct dielectric planarization agent and as a buff after tantalum-based barrier removal. The low downforce window of 1.0–3.0 psi is deliberate; for ultra-low-k films with k ≈ 2.2, cohesive failure or cap delamination has been observed on production tools when downforce exceeds 3.0 psi. Slurry flow below 100 mL/min can cause pad drying and increased microscratches, while flow above 300 mL/min may create non-uniform edge removal. Pad conditioning with a diamond disk is still required to maintain removal-rate stability, but the EL-grade slurry is generally less aggressive than fumed-silica slurries and may permit reduced conditioning downforce. The product is dispensed through point-of-use filtration with a 0.1 µm or 0.2 µm polypropylene filter; filtration pressure above 15 psi should be avoided because shear-induced aggregation can raise large particle count.

    The migration kinetics of sodium and potassium in porous low-k films are accelerated by absorbed moisture and electric fields at elevated temperature. Even at 100 ppb levels in the slurry, alkali metals can accumulate at the dielectric/cap interface during subsequent thermal processing if post-CMP cleaning is incomplete. The EL-grade specification therefore pairs the slurry with a cleaning requirement that includes dilute ammonium hydroxide or organic acid residue removal. The product itself is not a cleaning solution and does not eliminate the need for post-polish clean.

    When the Process Window Shifts to Selective Removal Against SiCN and TEOS

    Selectivity between the low-k dielectric and the adjacent cap layer defines the usable process window during dielectric planarization. A moderate low-k:SiCN selectivity of 2:1 to 5:1 on blanket films is maintained by the weakly alkaline colloidal silica chemistry. Under identical polishing conditions, the silicon carbonitride removal rate is typically below 25 nm/min when the low-k removal rate is 40–120 nm/min. The exact ratio is not universal because the SiCN composition, density, and post-etch surface condition vary with the integration scheme. On 300 mm blanket wafers, selectivity is measured by comparing thickness loss using spectroscopic ellipsometry before and after polishing. Published data for this specific configuration is limited for patterned wafers; end users must qualify the selectivity on the exact cap layer and low-k stack.

    When the cap is TEOS oxide instead of SiCN, the same slurry usually exhibits higher cap removal because dense silicon oxide is chemically and mechanically similar to the carbon-doped low-k surface. In such cases, the selectivity may fall below 2:1, and the polishing time or downforce must be reduced to prevent cap erosion. The EL-grade product is not supplied with field-adjustable oxidizer or inhibitor additives for modifying selectivity. Modifying the formulation outside the qualified pH window can destabilize the colloidal silica and invalidate large-particle-count control.

    Post-polish defectivity is measured by laser-scanning surface inspection at 90 nm sensitivity. On blanket carbon-doped oxide, adder counts after buff are usually below 50 adders per wafer for particles larger than 90 nm when the slurry is used within specified flow and conditioning parameters. Patterned-wafer defectivity is more sensitive to cap erosion and low-k fracture; the primary failure modes are delamination at the low-k/cap interface, line-edge roughness after copper exposure, and silica residue within open pores. Cleaning after polishing is performed with megasonic-assisted dilute ammonium hydroxide in a brush scrubber, followed by deionized water rinse and spin-dry. Incomplete residue removal can raise the effective dielectric constant of porous low-k film because adsorbed water and silanol groups in the open-pore network increase polarizability and degrade circuit delay. The electronic/EL grade is therefore formulated to minimize sub-0.1 µm particles that are difficult to remove from porous dielectric surfaces.

    From a production logistics standpoint, batch-to-batch pH drift is controlled to ±0.1 units and conductivity to ±10% of the nominal value. On high-volume CMP lines, a pH shift of 0.2 units has been correlated with a removal-rate variation of more than 20% on carbon-doped oxide, which is outside advanced-node process control limits. The slurry is supplied ready to use; dilution is not recommended because it changes ionic strength and particle surface charge. If agitation is required after shipping, low-shear rolling is sufficient. The product must not be frozen. Freeze-thaw cycling can cause irreversible colloidal aggregation and raise large particle count above the 50 particles/mL limit, potentially clogging 0.1 µm point-of-use filters. Storage in unopened containers at 15–25 °C is recommended. Direct mixing with acidic barrier slurries, hydrogen peroxide, or persulfate-containing oxidizer slurries in the same delivery line may cause silica aggregation or surface-charge alteration and should be avoided unless compatibility data for the specific mixture is available.

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