| HS Code | 568595 |
| Product Type | Positive-tone photoresist |
| Chemical Base | Novolac resin with diazonaphthoquinone (DNQ) photoactive compound |
| Physical State | Liquid at room temperature |
| Color | Amber to reddish-brown |
| Solvent | PGMEA (propylene glycol monomethyl ether acetate) |
| Viscosity | Typically 2 to 50 mPa·s at 25°C depending on grade |
| Exposure Wavelength | Optimized for i-line (365 nm), useful in 350–450 nm range |
| Sensitivity | High sensitivity suitable for LCD patterning at moderate exposure doses |
| Resolution | Capable of sub-micron resolution, down to approximately 0.8 µm |
| Contrast | High contrast with steep sidewall profile formation |
| Developer Compatibility | Compatible with metal-ion-free (MIF) TMAH-based developers |
| Thermal Stability | Stable through typical post-exposure and hard bake processes up to 130–150°C |
As an accredited LCD Photoresist Merck AZ-2000 factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.
| Packing | Packaged in 1-liter amber glass bottles with airtight, light-protective seals, ensuring safe transport and storage of Merck AZ-2000 LCD photoresist. |
| Container Loading (20′ FCL) | 20′ FCL of LCD Photoresist Merck AZ-2000, loaded upright in sealed drums, secured with dunnage, labeled, with spill containment. |
| Shipping | Ship as UN1993, Flammable Liquid, N.O.S. (contains propylene glycol methyl ether acetate), Hazard Class 3, Packing Group II. Use approved, grounded containers, protect from heat/ignition sources, and keep away from oxidizers. Provide SDS, proper marks/placards, segregation, and secure upright loading. Not marine pollutant. |
| Storage | Store Merck AZ-2000 LCD photoresist in its original, tightly sealed container in a cool, dry, well-ventilated area away from direct sunlight, UV light, heat, and ignition sources. Recommended storage temperature is 15–25°C. Keep container upright to prevent leaks. Inspect regularly; dispose of expired material safely per local regulations. |
| Shelf Life | Shelf life is typically 12 months from manufacture date when stored unopened, tightly sealed, in original container below 25°C. |
The application of Merck AZ-2000 in LCD manufacturing follows the flat-panel photolithography sequence: cleaning, adhesion promotion, resist coating, prebake, mask alignment, exposure, post-exposure bake, development, hard bake, etching or curing, and stripping or final permanence. The material is handled as a liquid resist blend with controlled viscosity and solids content; each downstream segment imposes different thickness, resolution, optical density, thermal budget, and adhesion requirements. The following scenarios are restricted to established TFT-LCD array fabrication, colour-filter-on-glass processing, photo spacer formation, via opening, and transparent electrode routing. No application outside flat-panel display lithography is assigned to this product article.
When AZ-2000 is used as an etch mask for thin-film transistor source/drain metal patterning, the controlling variable is sidewall integrity of a 1.5–2.0 µm dried resist line after wet etching in phosphoric-acetic-nitric acid at 40–45°C. Compliance in this segment is driven by SEMI S2 and SEMI S8 equipment safety evaluations for coater/developer and wet etch tools, ISO 14644-1:2015 Class 5 cleanroom operation, and RoHS 2011/65/EU Annex II homogeneous-material limits for lead and cadmium in final metal films. The resist is applied at 25–30 wt% solids; propylene glycol monomethyl ether acetate dilution is restricted to 0.5–2.0 wt% because higher dilution lowers photoactive compound loading and widens critical dimension uniformity beyond ±0.2 µm. In production, a Gen 8.5 glass sheet of 2200 mm × 2500 mm is cleaned, treated with HMDS at 0.05–0.10 wt% in PGMEA, coated by slit die to the target dried thickness, vacuum-dried, and soft-baked at 90–110°C for 60–120 s. Exposure is carried out with an i-line large-area scanner at 365 nm and 80–150 mJ/cm², followed by development in 2.38 wt% tetramethylammonium hydroxide for 60–90 s and hard bake at 130–150°C for 120–180 s. The hard-baked resist must withstand mixed acid penetration at the interface without lifting; failure commonly appears as localized voids above molybdenum or titanium underlayers. Finished product categories include TFT-LCD modules for desktop monitors, notebook panels, industrial displays, and automotive instrument clusters.
Black matrix processing on Gen 8.5 colour-filter lines uses AZ-2000 as a permanent light-shielding imaging layer with an optical density no lower than 3.0/µm at a cured thickness of 0.8–1.2 µm. Compliance requires RoHS 2011/65/EU Annex II limits for cadmium at ≤100 ppm and hexavalent chromium at ≤1000 ppm in the homogeneous cured film, REACH (EC) No 1907/2006 Article 33 communication for any substance of very high concern above 0.1 wt%, and IEC 61747 series display device performance validation. Formulation addition is controlled by pigment loading at 30–50 wt% of solids, acrylic binder at 20–35 wt% of solids, multifunctional monomer at 5–15 wt% of solids, and photoinitiator at 0.5–2.0 wt% of solids; PGMEA dilution before slit coating is held to 0.5–1.5 wt% to avoid edge-drying and mura. The production sequence includes slot die coating, vacuum drying at ≤100 Pa, soft bake at 90–110°C for 90–120 s, mask exposure at 100–250 mJ/cm², development in 2.38 wt% TMAH, and final curing at 220–240°C for 30 min. On large-area slit coaters, the shadow effect from the die lips and the mask aligner can produce peripheral optical density drift; in high-humidity lines above 60% RH, substrate pre-drying at 110°C for 60 s before coating is mandatory. Terminal product types are colour-filter glass for high-resolution mobile TFT-LCDs, notebook, tablet, and television panels.
In colour-filter-on-glass production, AZ-2000 is formulated as a pigment-dispersed imaging layer in which the resist vehicle carries red, green, or blue pigment paste; unlike an etch mask, the layer remains in the final device and must survive alignment-mark cleaning, planarization, and indium tin oxide sputtering. The applicable compliance set includes RoHS 2011/65/EU Annex II limits for lead, cadmium, mercury, and hexavalent chromium in each colour resist film, REACH (EC) No 1907/2006 Annex XVII restrictions for organic solvents and specific pigments, and ISO 14644-1:2015 Class 5 for coating and exposure areas. Formulation addition ratios are governed by colour-resist film properties: pigment concentration is 30–60 wt% of solids, acrylic binder is 10–30 wt% of solids, polyfunctional acrylate monomer is 5–15 wt% of solids, photoinitiator is 1–5 wt% of solids, and PGMEA is 30–50 wt% of total liquid formulation; to reach a 1.5–3.0 µm cured film, additional PGMEA is limited to 0.5–2.0 wt% based on viscosity measured at 25°C by ASTM D2196-20. The production process is repeated sequentially for RGB: slit die coating, vacuum dry, prebake at 90–110°C for 90–120 s, i-line exposure at 100–300 mJ/cm² through chromium-on-glass masks, aqueous alkali development with 0.04–0.05 wt% potassium hydroxide or 2.38 wt% TMAH, and post-bake at 230°C for 20–30 min to stabilize chromaticity and prevent yellowing. Amine contamination in the coater/developer cleanroom must remain below 5 ppb to prevent scum and latent image degradation. Terminal products include colour-filter substrates for TFT-LCD modules in smartphones, tablets, automotive dashboard displays, monitors, and television panels.
Dimensional stability after hard bake is the limiting variable in photo spacer arrays because cell gap uniformity across a Gen 8.5 substrate must remain inside ±0.1 µm to avoid mura and electro-optic distortion. Compliance is tied to IEC 61747 series LCD cell gap and optical test methods, ISO 14644-1:2015 Class 5 cleanliness, and SEMI S2/S8 coater/developer safety. The formulation addition ratio for a photo spacer build involves 30–40 wt% total solids, with epoxy or acrylate crosslinker content at 3–8 wt% of solids and PGMEA or PGME diluent at 2–5 wt% to achieve a viscosity of 12–25 cP at 25°C. Spacer production begins with direct slit die coating of a 3.0–5.0 µm dry film, followed by soft bake at 100–110°C for 120 s, mask exposure at 150–300 mJ/cm², post-exposure bake at 100–120°C for 60–90 s, development in 2.38 wt% TMAH, and a hard bake at 230°C for 30 min. Profilometer or interferometric measurement after hard bake is compulsory because shrinkage above 5% of initial thickness creates edge collapse and spacer-tip rounding. On actual production lines, batch-to-batch variance is controlled by maintaining the slit die gap at 100–200 µm, exhaust airflow at 0.3–0.5 m/s, and hotplate uniformity at ±1°C; a deviation in hard bake temperature of more than 3°C across the sheet shifts spacer profile outside specification before any electrical defect is visible. Terminal products are TFT-LCD panels with fixed cell gap for VA, IPS, and fringe-field switching modes in televisions, monitors, notebooks, and automotive displays.
Contact via patterning imposes vertical sidewall and resist adhesion requirements that differ from metal etch masks because the underlayer is an organic planarization film with high surface roughness and moisture uptake. Compliance requires ISO 14644-1:2015 Class 5, SEMI S2, and RoHS 2011/65/EU for final module materials. The resist is dispensed at 25–30 wt% solids; diluent addition with PGMEA is capped at 1.0–2.0 wt% to prevent swelling of the organic planarization layer. In production, the planarized backplane is dehydration-baked at 110°C for 60 s, coated to 2.0–4.0 µm dry resist thickness, prebaked, exposed with i-line radiation at 80–200 mJ/cm², developed in 2.38 wt% TMAH, and then dry-etched in an O2/CF4 plasma at 13.56 MHz RF power density between 0.3 W/cm² and 0.6 W/cm² to open via holes through the planarization layer. The resist is stripped in an amine-containing remover only after via inspection confirms complete removal of the planarization material from the underlying metal pad. Published AZ-2000-specific data for this plasma process configuration is limited; the stated power density must be requalified on the actual etch platform because variations in chamber electrode spacing and gas flow distribution alter the via taper angle. Terminal finished products include TFT backplanes used in high-resolution liquid crystal displays for monitors, medical displays, and avionics panels.
For indium tin oxide electrode routing, the resist layer is maintained as a sacrificial etch mask for a sputtered ITO film with sheet resistance of 10–30 Ω/sq; the main failure mode is undercutting of line edges if adhesion is not controlled before wet etching. Compliance is covered by IEC 61747 display panel qualification, ISO 14644-1:2015 Class 5, and RoHS 2011/65/EU for the final module. Formulation addition ratio is set at 25–30 wt% solids with PGMEA dilution no more than 0.5–1.5 wt%; an adhesion promoter such as HMDS is applied at 0.02–0.05 wt% in carrier solvent before coating to reduce edge pullback. The process includes slit die coating to 1.2–2.0 µm, soft bake, UV exposure at 80–150 mJ/cm², development in 2.38 wt% TMAH, post-bake at 130–150°C for 120–180 s, and wet etching in oxalic acid at 35–45°C; the resist is then stripped with an amine-free solvent system to avoid tin oxide residue on the patterned glass. Terminal product types include ITO-patterned colour-filter substrates and touch-sensor liquid crystal panels for industrial human-machine interfaces, point-of-sale displays, and automotive centre-stack modules.
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Merck AZ-2000 is a positive-tone, novolak/diazonaphthoquinone photoresist supplied for thin-film transistor array photolithography on flat glass substrates. The product is formulated for slot-die or spin coating, broadband g-, h-, and i-line exposure, aqueous alkaline development, and wet-etch patterning of gate and source/drain metallization. Film thickness after prebake is controlled by solids content and coating parameters; typical display production grades range from 1.0 µm to 2.5 µm. The product is used in active-matrix liquid crystal display manufacturing, where resist film uniformity, metal adhesion, strippability, and mobile-ion contamination are controlling variables.
In a production environment, lot-to-lot viscosity is monitored with a cone-plate viscometer at 25°C; the viscosity range is grade-dependent. The solvent system is selected for compatibility with slit-die coaters and for controlled evaporation during prebake. Lot release data typically include solids content, viscosity, film thickness at a reference spin speed, trace metal content, and particle counts. The product is supplied in clean-room-compatible packaging and is filtered to control sub-micron particle defects. Exposure chemistry follows the standard diazonaphthoquinone mechanism: the photoactive compound converts to a carboxylic acid in exposed areas, enabling development in 2.38% aqueous tetramethylammonium hydroxide.
Compared with general semiconductor i-line resists, AZ-2000 is adjusted for large-substrate exposure tools and for the dimensional tolerances of display thin-film transistors. Critical dimensions in mass production are typically 2–5 µm, with overlay and CD uniformity requirements driven by panel-level yields. Because this product is applied to substrates that can exceed 2,200 mm in width, coating and drying behaviour are designed to avoid edge-bead discontinuities and striations that would generate open lines or shorts in gate and data interconnects.
Representative release ranges reported for display photoresist grades of this class are summarized in the following table; the AZ-2000 certificate of analysis for the selected viscosity grade is the controlling document.
| Parameter | Test method | Typical value or range |
|---|---|---|
| Film thickness after prebake | Spin curve at 3,000 rpm, 25°C; hot plate 100°C/90 s | 1.0–2.5 µm |
| Viscosity at 25°C | ISO 2884-3 cone-plate | 5–25 mPa·s according to grade |
| Solids content | ASTM D2369 gravimetric | 15–30 wt% according to grade |
| Sodium content | ICP-MS after ashing | <100 ppb |
| Potassium content | ICP-MS after ashing | <100 ppb |
| Total metal contamination | ICP-MS after ashing | <500 ppb |
| Particle count ≥0.3 µm | Laser particle counter | <50 particles/mL |
The fundamental diazonaphthoquinone-novolak chemistry is shared with many semiconductor i-line resists; however, the additive package and solvent blend are modified for flat panel display processing. Conventional i-line resists are often optimised for wafer-level spin coating, for CD targets below 1 µm, and for plasma-etch selectivity. AZ-2000 is formulated for larger thicknesses, for wet-etch resistance against hot phosphoric/acetic/nitric acid aluminium etchants, and for adhesion to sputtered molybdenum, aluminium, and indium tin oxide. The product also exhibits lower dark erosion during puddle development, which preserves linewidth after long developer residence times on large panels.
A second difference is the mobile-ion budget. Thin-film transistor channel regions are sensitive to sodium and potassium contamination because field-effect electrical thresholds shift under bias-temperature stress. Semiconductor-grade resists may have sodium specifications in the low-parts-per-million range; display-grade AZ-2000 is controlled to low-parts-per-billion levels by inductively coupled plasma mass spectrometry to prevent threshold voltage drift. The product is also formulated to minimise residue after stripping on glass substrates; residual carbon and inorganic ash can degrade passivation adhesion and subsequent indium tin oxide deposition uniformity.
| Characteristic | AZ-2000 display positive resist | Conventional i-line positive resist | Negative-tone nLOF 2000-series resist |
|---|---|---|---|
| Tone | Positive | Positive | Negative |
| Primary chemistry | Novolak/diazonaphthoquinone | Novolak/diazonaphthoquinone | Crosslinking i-line formulation |
| Target substrate | Large-format glass panels | Semiconductor wafers | Wafer-level lift-off and thick films |
| Typical film thickness | 1.0–2.5 µm | 0.5–2.0 µm | 2–10 µm |
| Developer | 2.38% TMAH | 2.38% TMAH | 2.38% TMAH |
| Main processing route | Wet-etch array metallization | Plasma or wet-etch wafer patterning | Lift-off or electroplating |
In slit-die coating of generation 8.5 substrates, the resist is pumped through a precision slot nozzle with a lip gap of 50–150 µm while the glass moves at 3–5 m/min; the wet film is then dried on a hot plate or in a convection oven. In spin coating on smaller substrates, dispense is followed by a spin speed ramp to 1,500–3,000 rpm. Coating-room temperature and relative humidity are controlled because solvent evaporation rate determines edge-bead height and film thickness uniformity.
Typical hot-plate prebake is 100°C for 90 s; convection oven conditions for thicker films may range from 90–110°C for 10–20 min. Underbaking leaves residual solvent, causing attack during wet etch and reduced adhesion. Overbaking can reduce sensitivity and increase scum after development. Exposure energy is generally 40–120 mJ/cm² at i-line, with the exact dose dependent on film thickness, prebake, and exposure tool optics. Development in 2.38% tetramethylammonium hydroxide at 22–24°C for 30–90 s is typical in puddle or spray equipment. Qualified production lots exhibit dark erosion below 10% of initial film thickness during the specified development cycle.
Adhesion is evaluated on sputtered aluminium/molybdenum test parts by crosshatch tape pull according to ASTM D3359; minimum rating 4B is common for production qualification. Film thickness uniformity on coated panels is measured by optical interferometry at multiple fixed locations. A production lot is typically held to a thickness range of ±3% of target before exposure; out-of-range material is stripped and reworked before pattern transfer.
Mobile-ion contamination is controlled because sodium and potassium drift into the gate insulator under applied bias. Resists are qualified by inductively coupled plasma mass spectrometry after ashing. Typical upper limits for AZ-2000 display grades are 100 ppb sodium, 100 ppb potassium, and 500 ppb total metals. The product is filtered through sub-micron filters during manufacture; particle counts are measured by laser light scattering at fill and at point of use.
Defect density on coated panels is influenced by resist microgels, filter shedding, and inadequate substrate cleaning. In production, automated optical inspection is used after development. A resist-related defect density above 0.1 defects/cm² may trigger lot quarantine on array lines. Batch-to-batch variance is controlled by blending to kinematic viscosity targets and by maintaining solvent balance; small shifts in solvent composition alter drying rate and edge-bead profile.
Compatibility with process equipment is evaluated with accelerated stress tests. For example, resist samples stored at 40°C for 72 h must not form gel particles or shift viscosity by more than 5%. Operational boundaries include storage at 5–25°C, exclusion of ultraviolet radiation, and use in ventilated coating areas. The Safety Data Sheet is the controlling document for hazard and handling requirements under REACH Regulation (EC 1907/2006).
On an active-matrix array line, adhesion failure signatures after wet etching are observed as undercut at the etch bath inlet, lifted resist edges along sputtered aluminium grain boundaries, and CD bias non-uniformity between panel centre and edge. For AZ-2000, adhesion to molybdenum and aluminium begins with substrate dehydration and organosilane or hexamethyldisilazane priming; a prebake below 100°C or a coating-room relative humidity above 60% increases the incidence of lifting. The resist is exposed with a mask aligner or scanner, developed in 2.38% tetramethylammonium hydroxide, and the pattern is transferred into the metal stack by hot phosphoric/acetic/nitric acid etch at 40–50°C. Etch times on a commercial batch etcher can exceed 120 s, and the resist must maintain adhesion throughout the etch cycle without cracking or peeling.
Stripper compatibility is specified with the panel fabrication plant’s stripping tool. Spray processors operate at 50–70°C with amine-based organic strippers; complete removal is verified by contact angle measurement and by optical inspection. Incomplete stripping is not typical for this material but may occur if postbake exceeds 130°C or if the resist is exposed to fluorine-based plasma before strip; such processes require oxygen plasma descum or a solvent pre-rinse. Rework loops for coating defects use either spin cleaning with fresh solvent before bake or complete strip after develop. In a spray strip process, removal is normally achieved in 60–120 s.
Amine contamination in cleanroom air can neutralize the surface acid formed during exposure and produce a partially insoluble skin in positive diazonaphthoquinone resists. The resulting T-topping or scum causes opens in small spaces and is aggravated by delays between exposure and development. For AZ-2000, the formulation is adjusted to reduce surface inhibition; the product is qualified on production lines where cassette residence time between exposure and development can extend to 4 h at 23°C and 50% relative humidity. If post-exposure delay exceeds the qualified window, linewidth shift in 3 µm features appears as feature narrowing and increased residual surface skin.
The process window is not unlimited. In facilities with ammonia-containing cleaning agents, even shorter delays can produce residues. Published data for this specific configuration is limited, and a recommended maximum post-exposure delay is stated in the lot-specific process note. Exposed panels should be developed within the validated time, and split-lot qualification is necessary when changing exposure tools or developer nozzle configuration.
In comparison with negative-tone resists used in lift-off or electroplating, AZ-2000 does not require a crosslinking post-exposure bake and does not exhibit solvent-swelling during development. Pattern fidelity is controlled instead by exposure dose, prebake temperature, and development time. The positive-tone platform provides compatibility with conventional display wet-etch transfer, but resolution capability narrows below approximately 1.5 µm; below that feature size, process latitude is reduced and the resist should be evaluated with the specific mask aligner and developer geometry.
