On a-Si:H TFT array substrates for LCD panels, AZ 1500 is coated as the primary wet-etch masking layer over sputtered Mo/Al/Mo or Mo/Cu/Mo source–drain metallization. The resist is applied at 100% as supplied through point-of-use 0.2 µm PTFE filters; no external resin or photoactive compound is compounded on site. A 10–16 mL dynamic dispense per Gen 4 sheet (730 mm × 920 mm) is followed by spin coating to a dry film thickness of 1.2–1.5 µm using AZ 1512HS or AZ 1518 on a closed-cassette TEL or DNS coat/develop track. Viscosity adjustment with AZ 1500 thinner is limited to 2–4 vol% when ambient exhaust raises measured kinematic viscosity above 35 cSt; dilution above 5 vol% produces statistically significant critical-dimension nonuniformity across the sheet edge under automated optical inspection. Soft bake uses a multi-zone conduction hotplate at 105 °C ±1 °C for 110–130 s; hotplate temperature drift below 100 °C causes scumming after development, while local overshoot above 112 °C causes thermal crosslinking that increases strip residue. The resist is patterned with proximity g/h/i-line exposure at 200–350 mJ/cm²; dose selection follows a swing curve generated for each resist lot, with the first thickness minimum occurring between 0.75 µm and 1.0 µm. Development in 2.38 wt% TMAH at 23 °C ±0.5 °C for 75 s ±10% produces line/space resolution of 1.5 µm across the array. The subsequent wet etch uses a phosphoric–acetic–nitric acid mixture at 38–42 °C; resist adhesion must survive a bath residence of 180–240 s without lifting at Mo grain boundaries. Stripping is performed in inhibited NMP/DMSO-based strippers at 70 °C, followed by DI rinse and hot-air dry. Cleanliness is maintained to ISO 14644-1:2015 Class 5 in coating, exposure, and wet-bench areas, and equipment safety interlocks are validated to SEMI S2-0718a. Terminal product types include LCD television panels, desktop monitors, automotive dashboard displays, and industrial HMI modules.

What Process Limits Govern ITO Electrode Patterning for In-Cell Touch LCD Stacks?

ITO transparency and low sheet resistance impose a narrower process window when AZ 1500 is used as the etch mask on capacitive touch sensor electrodes. The resist is dispensed at 100% as received; for film thickness below 1.2 µm, dilution with PGMEA is restricted to ≤3 vol% because higher solvent fractions reduce diazonaphthoquinone concentration and enlarge dark erosion during development. Target dry film thickness over ITO step edges is 1.5–2.0 µm using AZ 1518 at 2200–2800 rpm; coat speed is lower than for planar metal etch masks to accommodate the 50–200 nm ITO step height without forming edge beads along the display active area. Soft bake at 100 °C for 120 s is followed by broadband exposure at 250–350 mJ/cm²; underexposure below 180 mJ/cm² leaves residual resist after development in 2.38 wt% TMAH, while overexposure above 420 mJ/cm² produces excessive scumming at the ITO etch front. A 30–60 s oxygen-plasma descum at 70–100 W before wet etching reduces adhesion failure in oxalic acid or mixed HCl/HNO3 etchants; pinhole density increases if post-exposure delay exceeds 45 min under cleanroom airflow below 45% RH. Etching of ITO is conducted at 40–45 °C in acid systems buffered to minimize undercut; endpoint is detected optically when the sheet resistance of the exposed ITO disappears. After stripping, adhesion is classified by ASTM D3359-17 Method B; production lots are rejected below classification 4B. The relevant compliance set includes ISO 14644-1:2015 Class 5 for particle control and IEC 62474:2018 for declarable substance thresholds in the final touch stack. Terminal product types are in-cell touch smartphone LCD assemblies, tablet displays, automotive center-stack panels, and industrial touch monitors.

Chrome black matrix layers on color filter substrates for VA and IPS LCDs are subtractively etched after AZ 1500 lithography; the resist must maintain sub-1 µm critical-dimension fidelity across a 0.3–0.8 µm chromium oxide/chrome stack without lifting during ceric ammonium nitrate wet etch. For this configuration the resist is used as supplied with no added active components; if thickness reduction is needed to improve expose throughput, AZ 1500 thinner is added at 4–6 vol% only under closed-loop viscosity control, because dilution beyond 6 vol% degrades sidewall angle below 70° and exposes chrome edges to undercut. Coating is performed at 3000–3800 rpm to achieve 0.9–1.1 µm dry film on non-alkali glass; bake temperature is lowered to 95 °C for 150 s to avoid thermal stress between the chrome layer and glass. Exposure uses a g/h-line mask aligner at 120–220 mJ/cm², and development in aqueous TMAH at 2.38 wt% for 50–65 s clears the patterned areas. The wet chrome etch proceeds in ceric ammonium nitrate at 30–35 °C until endpoint; resist residues after etch are removed with sulfonic-acid strippers followed by O2 plasma ashing at 200–300 W. Cleanroom operation is qualified to ISO 14644-1:2015 Class 5, safety-data-sheet communication is maintained under REACH Regulation (EC) No 1907/2006, Article 31, and the final color filter sub-assembly is assessed under EU RoHS Directive 2011/65/EU, Annex II homogeneous material limits. Terminal products are LCD color filter arrays for televisions, notebook panels, and medical display screens.

Dry-Etch Masking of Silicon Nitride Passivation in a-Si TFT Arrays

Silicon nitride passivation etch on a-Si TFT arrays uses AZ 1500 as a thick sacrificial mask because plasma etch selectivity of resist to SiNx in fluorine-containing discharges can fall below 1:1, demanding a resist thickness of 2.0–2.5 µm to survive etch time while retaining post-etch strip morphology. The resist is applied undiluted at 100% as supplied; adding AZ 1500 thinner above 2 vol% is not permitted because the consequent film thickness loss shifts etch bias beyond the gate-line critical-dimension tolerance. Spin coating at 1800–2200 rpm with AZ 1518 yields the required thickness, followed by soft bake at 105 °C for 180 s on a non-contact hotplate to remove residual PGMEA. A g/h/i-line stepper exposes the via pattern at 280–400 mJ/cm²; post-exposure bake is omitted for this dielectric mask to avoid altering DNQ development kinetics. Development in 2.38 wt% TMAH at 23 °C for 90–120 s terminates before dark erosion exceeds 50 nm. Plasma etch is performed in a reactive-ion etcher at 100–200 mTorr using CHF3/O2 or SF6/O2 chemistry; the resist erodes at approximately 1.0–1.5 µm during a 2.5–3.0 µm SiNx removal, leaving a residual mask that is stripped in oxygen plasma. Adhesion failures at via edges are controlled by a descum step of 60 s at 100 W. Equipment interoperability follows SEMI S2-0718a for vacuum interlocks and exhaust gas abatement; cleanroom particulate limits follow ISO 14644-1:2015 Class 5. Terminal products include thin-film transistor arrays for LCD monitors, automotive navigation displays, and point-of-sale terminal screens.

Liquid crystal on silicon (LCoS) microdisplays require a reflective pixel array on 200 mm or 300 mm silicon wafers; AZ 1500 is used to pattern the aluminum reflective electrode layer with pixel pitches of 8–10 µm. In this process the resist is undiluted; an HMDS vapor prime at 125 °C for 60 s precedes coating. The formulation addition is controlled by weight: 100 parts AZ 1500 as supplied to 0 parts external solvent in production, with point-of-use filtration at 0.1 µm PTFE to remove microgels that otherwise print as micrometer-scale comets on the array. AZ 1512HS is spin coated at 3500–4200 rpm to 1.0–1.2 µm; soft bake at 100 °C for 90 s drives residual PGMEA below 0.5 wt%. Exposure at i-line 365 nm uses a 5× reduction stepper with 200–300 mJ/cm²; after development in 2.38 wt% TMAH for 60–70 s, the aluminum reflector is wet-etched in phosphoric–acetic–nitric acid or dry-etched in a Cl2/BCl3 inductively coupled plasma at 20–30 mTorr. A deep ultraviolet hardening step at 120 °C for 120 s is applied where dry-etch loading is high. Cleanliness for the LCoS photolithography cell is qualified to ISO 14644-1:2015 Class 4, with particle monitoring per ISO 14644-2:2015; material compliance is documented under REACH Article 31 and EU RoHS 2011/65/EU. Terminal product types are LCoS pico-projectors, automotive AR head-up display engines, and embedded smart-glasses light modulators.

When Display Module Bonding Pads Require Patterning on Chip-on-Glass Driver Interposers

COG and COF display driver interposers use AZ 1500 to pattern electroplated gold bumps or copper redistribution lines on 8-inch silicon or polyimide reel-to-reel formats. The resist is delivered at 100% as received to the manufacturing line; when electroplating thickness exceeds 10 µm, AZ 1500 thinner is added at 0–3 vol% to lower viscosity and improve leveling over non-uniform copper seed layers, but dilution must not exceed 3 vol% because bottom scumming after development causes poor electroplating uniformity. Coating on polyimide carriers proceeds at 1500–2500 rpm to achieve 3.0–4.0 µm dry films with AZ 1518; soft bake at 95 °C for 120 s avoids polyimide outgassing. Exposure with a broad-spectrum g/h/i-line contact aligner at 300–450 mJ/cm² is followed by puddle development in 2.38 wt% TMAH for 100–140 s, yielding mold openings with 85–88° sidewalls suitable for gold electroplating. Published data for exact sidewall angle distribution on reel-to-reel formats is limited; the specified 85–88° range derives from in-line production lot qualification rather than a single standardized method. Electrodeposition uses a neutral cyanide-free gold sulfite bath at 60 °C and 2–4 mA/cm²; resist lift-off after plating uses NMP-based stripper at 70 °C. Compliance is maintained to ISO 14644-1:2015 Class 5 for roll-to-roll handling and SEMI S2-0718a for wet bench safety; substance declaration is managed under IEC 62474:2018. Terminal product types include COG driver ICs for automotive displays, COF tape packages for OLED panels, and high-density flex-on-glass interposers.