Dongjin Semichem DJR-100 is supplied as a negative-tone acrylic photoresist for LCD photolithography. The following application scenarios document qualified downstream uses where DJR-100 is processed on production-scale coating, exposure, and development equipment. Each scenario identifies the governing compliance requirement, the applicable formulation addition ratio or solids condition, the production process sequence, and the terminal finished product type. Where DJR-100-specific public data is limited for a given configuration, the description identifies the comparable production window and does not assign an unverified fixed value.

What Limits Post-Exposure Bake Crosslink Uniformity When DJR-100 Is Slot-Die Coated on 5.5-Generation Glass?

In RGB color filter production on 1300 mm × 1500 mm glass, DJR-100 is filtered to 0.45 μm absolute before entering a slit-die coating head. The industry compliance standard applied at this stage is ISO 14644-1:2015 airborne particulate class ISO 7 in the coating bay and ISO 6 at the in-line edge-bead removal zone; RoHS Directive 2011/65/EU Annex II material limits are verified by IEC 62321-5:2013 for lead and cadmium below 0.1 % w/w and 0.01 % w/w respectively. The formulation addition ratio is not a post-arrival reactive dilution: the resist is used as supplied at 2.5–5.5 mPa·s at 25 °C, and only PGMEA is added up to 3 wt% when coating-dry film thickness must be reduced below 1.0 μm; pigment solids in the wet film remain between 18 wt% and 28 wt%, with photoinitiator content at 2.0–4.5 wt% relative to total solids. The downstream production process begins with low-pressure pump transfer through a 0.1 μm point-of-dispense filter, followed by slot-die coating at a gap of 60–120 μm, a wet film thickness of 1.4–2.2 μm, and a prebake at 90–110 °C for 120–180 s in a vacuum-dry oven. Exposure uses i-line 365 nm proximity or mirror projection systems at 30–70 mJ/cm², followed by post-exposure bake at 110–120 °C for 90 s; development in 0.4 wt% tetramethylammonium hydroxide at 23 °C for 60–90 s removes unexposed regions, and final post-bake at 230 °C for 30 min fixes the RGB pattern. The terminal finished product type is the pigmented pixel array on color-filter glass that is laminated to TFT array substrates in LCD modules for monitors, notebook panels, and mid-size automotive displays.

Black-matrix photolithography using DJR-100 imposes an optical-density boundary that is not satisfied by simple pigment loading: optical density after final cure must reach ≥4.0 at 550 nm while panel-level reflection remains below 5% across visible wavelengths. The governing compliance requirement is optical density measured by ISO 13468-1:2019 total luminous transmittance using a D65 illuminant, with a maximum luminous transmittance of 0.5% at 1.0 μm cured film; adhesion is checked by ASTM D3359-17 cross-cut tape test to maintain 5B after water immersion at 85 °C for 24 h. Formulation addition ratio for this configuration uses carbon black at 6–12 wt% of total solids, an alkali-soluble acrylic binder at 55–70 wt% of total solids, and a multi-functional acrylate monomer at 10–20 wt% of total solids; PGMEA dilution is kept below 2 wt% because higher solvent load causes particle settlement in idle coating lines. Production equipment includes a spin coater or slit coater with an exhaust enclosure to control solvent dewetting, prebake at 90–100 °C for 100–150 s, i-line exposure at 40–80 mJ/cm² through a chrome photomask with subpixel critical dimensions of 2–6 μm, development in 0.4 wt% tetramethylammonium hydroxide for 50–70 s, and post-bake at 220–240 °C for 30–40 min in a nitrogen-purged oven to prevent surface oxidation. The terminal finished product is a black-matrix glass sheet with photopatterned light-shielding walls that define RGB subpixels in thin-film-transistor LCD panels, particularly for high-resolution smartphone and automotive cluster displays.

Photo Spacer Compressive Strain, TMAH Under-Development Margins, and Column-Density Limits in Cell Assembly

Photo spacer formation in liquid-crystal cell assembly requires an acrylic negative resist that can maintain column-foot width after development without collapsing adjacent features under one-drop-fill pressure. The applicable compliance framework includes ASTM D3359-17 for post-bake adhesion before and after liquid-crystal contact, and SEMI S2-0220 equipment safety provisions for photoresist coater and developer tools; dimensional uniformity is verified by non-contact white-light interferometry with a within-plate 3σ height spread of ≤0.15 μm on 1500 mm × 1850 mm glass. Formulation addition ratio for photo spacer columns uses total solids of 25–35 wt%, a negative acrylic resin system with epoxy or acrylate crosslinker at 8–15 wt% relative to total solids, and a photoacid generator or photoinitiator package at 3–6 wt% relative to total solids; no external silica or polymer beads are blended because the photoresist itself forms the pillar matrix. The downstream production process includes dehydration bake at 120 °C for 60 s, slit-die coating to a dry film of 2.5–4.0 μm, prebake at 90–110 °C for 120 s, i-line exposure at 50–100 mJ/cm² through a halftone or binary mask with spacer diameters of 8–20 μm and densities of 50–120 pillars/mm², post-exposure bake at 115–125 °C for 90 s, and development in 2.38 wt% tetramethylammonium hydroxide for 45–75 s; under-development is deliberately held near 10–15% of the pattern pitch to maintain column foot width without colloidal attack at the glass interface. Final post-bake at 230 °C for 30 min achieves the compressive modulus plateau needed for drop-fill and one-drop-fill processes. The terminal finished product type is the photo spacer array on color-filter or array glass that becomes the cell-gap control layer in thin-film-transistor LCDs for televisions, monitors, and high-ambient-temperature automotive clusters.

When an indium tin oxide transparent electrode is deposited by DC magnetron sputtering at 200–230 °C onto a color-filter stack, the underlayer must survive vacuum heat, sputter plasma UV, and wet processing without outgassing. DJR-100 is used in an overcoat configuration where the photosensitive acrylic is coated after blue-green-red pixel and black-matrix formation to planarize the 0.4–0.8 μm RGB topography before ITO deposition. Compliance is documented by ISO 13468-1:2019 for luminous transmittance ≥95% at 2.0 μm cured film, and by ASTM D3359-17 for 5B adhesion after 240 h at 85 °C/85% RH. The addition ratio in this layer differs from pixel resist: total solids are 20–28 wt%, thermal crosslinker is 5–10 wt% relative to total solids, photoinitiator is 1.5–3.0 wt% relative to total solids, and PGMEA-based thinner may be added up to 5 wt% only if slit-die gap control falls below ±0.05 μm wet-film tolerance. The production process uses a low-velocity slot-die coater with a downstream vacuum solvent-extraction chamber, prebake at 90–100 °C for 120 s, broadband or i-line exposure at 25–50 mJ/cm² because the unpigmented matrix has faster photokinetics than carbon-black formulations, development in 0.4 wt% tetramethylammonium hydroxide at 23 °C for 50–80 s, and hard-bake at 230 °C for 30 min under nitrogen. Terminal finished products are color-filter substrates with a planarized ITO-ready overcoat that are subsequently processed into touch-integrated LCD modules and high-resolution industrial panels.

When TFT Array Via Printing Transfers DJR-100 from Color-Filter Tooling to Contact-Hole Patterning, Which Resist Stripping Boundary Emerges?

In thin-film-transistor array fabrication for LCD backplanes, DJR-100 is applied as a negative i-line photoresist for contact-hole and via patterning in gate-insulator and passivation layers, provided that downstream stripping compatibility with amine-free solvent strippers is validated on the actual via chain. The applicable compliance standard set includes SEMI S2-0220 for coater/developer tool safety, ISO 14644-1:2015 Class ISO 4 in the exposure bay, and RoHS Directive 2011/65/EU Annex II limits for lead, mercury, and chromium, verified by X-ray fluorescence screening per IEC 62321-3-1:2013. The formulation addition ratio for array use is lower in viscosity than the color-filter condition: the resist is diluted with PGMEA to 1.8–2.5 mPa·s at 25 °C, corresponding to 3–6 wt% added thinner, while total solids remain 12–18 wt%; a photoacid generator is maintained at 2–4 wt% relative to total solids to balance sensitivity and dark erosion. The downstream production process includes hexamethyldisilazane vapor priming at 120 °C for 90 s, spin coating at 1200–2500 rpm to a dry film of 1.0–2.0 μm, prebake at 100–110 °C for 90–120 s, i-line stepper or proximity exposure at 20–45 mJ/cm², post-exposure bake at 110 °C for 60–90 s, and development in 2.38 wt% tetramethylammonium hydroxide with a single-puddle process for 40–60 s; stripping after etch uses a heated N-methyl-2-pyrrolidone-free stripper at 60–70 °C for 5–10 min. Published equipment data for DJR-100 in contact-hole configurations on amorphous silicon backplanes is limited; the values reflect process boundaries for negative i-line resists on the same tool set, not a supplier-guaranteed condition. The terminal finished product type is the TFT backplane with patterned contact holes that receives a-Si or IGZO semiconductor layers, ultimately assembled into high-resolution LCD panels for notebooks and monitors.

DJR-100 in color-filter-on-array integration is processed at a lower post-bake thermal budget than separate color-filter glass because the underlying source-drain metallization imposes a ceiling of 220 °C for 30 min. The governing compliance requirement is adhesion after multiple wetting and drying cycles, tested by ASTM D3359-17 cross-cut adhesion with a minimum 4B result after immersion in a liquid-crystal material at 60 °C for 72 h; RoHS Directive 2011/65/EU Annex II and REACH SVHC declarations are applied to the full coated substrate. Formulation addition ratio in color-filter-on-array lines is adjusted for lower pre-bake thermal mass and tighter surface topography: total solids are 20–25 wt%, pigment dispersion solids are 15–22 wt% relative to total wet film, and a free-radical initiator is held at 2–3 wt% relative to total solids; PGMEA is not added beyond 4 wt% because excess solvent promotes edge pullback over TFT step heights of 0.3–0.6 μm. The production process uses a 2.5-generation or 4.5-generation slot-die coater with active gap compensation, prebake at 80–90 °C for 150 s to avoid copper oxidation, i-line exposure at 25–50 mJ/cm², development in 0.4 wt% tetramethylammonium hydroxide at 22–24 °C, and final cure at 200–220 °C for 30 min under forced nitrogen. The terminal finished product type is a color-filter-on-array substrate that enters cell assembly without a separate color-filter sheet, enabling thinner and narrower-border LCD modules for mobile and automotive display applications.