| HS Code | 594512 |
| Product Name | TOK TSMR-5000 |
| Photoresist Type | Positive i-line photoresist |
| Base Resin | Novolak resin |
| Photoactive Compound | Diazonaphthoquinone (DNQ) |
| Exposure Wavelength | I-line, 365 nm |
| Solvent System | Ethyl lactate-based organic solvent |
| Appearance | Pale red-brown transparent liquid |
| Viscosity At 25c | 5.0 mPa·s (typical) |
| Resolution | 0.5 µm lines/spaces or finer (representative) |
| Film Thickness Application Range | 1.0 to 5.0 µm (typical) |
| Developer Compatibility | Aqueous TMAH developer, e.g. 2.38% |
| Etch Resistance | High |
| Contrast | High |
| Storage Temperature | Below 25°C, protected from light |
| Shelf Life | Typically 6 months from manufacture |
As an accredited I-line Photoresist TOK TSMR-5000 factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.
| Packing | Sealed in high-purity polyethylene or glass bottles, nitrogen-blanketed, typically supplied in 1-liter containers for safe handling. |
| Container Loading (20′ FCL) | 20′ FCL loading of I-line photoresist TOK TSMR-5000: securely stowed, hazard-compliant, ventilated containers, segregated, labeled, and braced for safe transit. |
| Shipping | Shipment of TOK TSMR-5000 I-line photoresist requires strict hazardous material compliance. Pack in original UN-approved containers, upright, with secure cushioning. Use ground or freight transport only, avoiding extreme heat and open flame. Include proper documentation, labeling, and MSDS; observe local dangerous goods regulations and prevent leaks or spills during transit. |
| Storage | Store TOK TSMR-5000 I-line photoresist in its original, tightly sealed container in a cool, dry, well-ventilated area away from direct sunlight and heat. Maintain recommended temperatures, typically 5–35°C; avoid freezing and open flames. Keep away from incompatible materials, and follow all handling and disposal guidance to preserve quality and safety. |
| Shelf Life | Shelf life is typically 12 months from manufacture date when stored upright at 5–25°C in original, light-tight containers. |
Copper pillar bump plating for fine-pitch wafer-level packages uses TSMR-5000 as a sacrificial plating mold in which the sidewall angle transfers directly to electroplated copper; therefore the resist profile must remain within 85°–90° after development and must not shift during plating bath immersion. The supplied material is a single-component DNQ–novolac positive-tone i-line resist in PGMEA and is processed at a point-of-use formulation ratio of 100% as-received resist, with PGMEA added only at ≤5 vol% for edge bead control or coater purge recovery because greater dilution reduces viscosity below the spin-coating window and promotes edge pullback on 300 mm wafers. Compliance review for this operation falls under SEMI S2-0720 for coating track safety integration, SEMI S10-0322 for process chemical dispensing and containment, and REACH EC 1907/2006 Article 33 SVHC communication where any candidate-list substance in the dried resist film exceeds 0.1 wt%. The downstream production sequence includes HMDS vapor priming at 110–130°C, static dispense of 3–8 mL, spin coating to a film thickness of 8–25 µm, hotplate soft bake at 100–120°C for 180–300 s, i-line exposure at 365 nm with a stepper or full-field aligner at 300–800 mJ/cm², post-exposure bake at 110–125°C for 60–120 s, puddle development in 2.38 wt% TMAH (0.26 N) for 120–300 s, oxygen descum at 100–200 W for 30–60 s, copper electroplating at 1.0–3.0 A/dm², tin-silver cap deposition, seed etching, and resist strip. The resulting terminal components are copper pillar/solder-capped wafer bumps for flip-chip chip-scale packages and system-in-package interconnects. The main production boundary is resist voiding over copper seed topography deeper than 5 µm when post-HMDS surface energy is insufficient; oxygen descum should remain below 60 s to avoid sidewall roughening in the plating bath.
| Parameter | Expected range |
|---|---|
| Single-coat thickness | 8–25 µm |
| Soft bake | 100–120°C, 180–300 s |
| I-line exposure dose | 300–800 mJ/cm² at 365 nm |
| Post-exposure bake | 110–125°C, 60–120 s |
| Developer | 2.38 wt% TMAH, 120–300 s |
| Oxygen descum | 100–200 W, 30–60 s |
In gold bump electroplating, the limiting defect is not exposure resolution but thickness uniformity across the wafer edge where plating current density rises. The point-of-use formula ratio is 100% photoresist; PGMEA dilution is kept at ≤2 vol% because gold cyanide or sulfite baths can extract low-molecular-weight novolac fragments from over-diluted films and cause surface crusting. The film thickness to gold bump height ratio is maintained at 1.2:1–1.5:1; a 12 µm gold bump therefore requires 14.4–18.0 µm of resist. Compliance is evaluated under IEC 62474:2023 material declarations for final bump metallization, RoHS 2011/65/EU Annex II restricted substance screening after stripping, and ISO 14644-1:2015 Class 5 cleanroom control for resist dispensing. The process flow includes HMDS priming, static dispense, spin coating, soft bake, 365 nm i-line projection, post-exposure bake, TMAH puddle development, oxygen descum, seed layer sputtering, gold electroplating at 0.3–1.5 A/dm², and resist stripping. Terminal components are gold stud bumps and Au bumps for LCD driver ICs, optoelectronic modules, and RF front-end assemblies. For cyanide-based gold baths, published data on TSMR-5000-specific compatibility are limited; a bath immersion test at 60°C for 8 h is required before full production because resist swelling above 8% thickness change creates mushroom-shaped deposits.
Via formation for 2.5D and 3D integration uses cyclic SF₆/C₄F₈ deep reactive ion etching, and the photoresist mask must maintain sufficient thickness to prevent breakthrough at the via rim. For through-silicon via depths of 50–100 µm, an initial TSMR-5000 mask thickness of 10–20 µm is used, but the specific etch selectivity of TSMR-5000 in a given etcher must be qualified because published selectivity data for this configuration are limited. The resist is applied without reactive dilution; only PGMEA rinse solvent at 0–2 vol% is used for spin-bowl edge rework because thinning the mask reduces the etch budget proportionally. Compliance is governed by SEMI S2-0720 for etch tool integration, ISO 14644-1:2015 Class 4 for via lithography, and REACH EC 1907/2006 for chemical registration of PGMEA. The downstream sequence includes HMDS priming over an oxide hard mask, coating and soft bake at 100–120°C, aligner exposure at 365 nm, post-exposure bake at 110–125°C, development in 2.38 wt% TMAH, oxide hard-mask opening, Bosch silicon etching at 10–20°C chuck temperature, and final resist removal. Terminal output comprises through-silicon via interposer wafers for high-bandwidth memory and logic-on-interposer assemblies. A critical constraint is that the resist should not be hard baked above 130°C before silicon etching because excessive crosslinking increases strip residue after plasma exposure and can reduce via bottom CD by blocking the opening during oxide etch.
High-brightness LED wafer lines on sapphire require thick metal pad plating masks that can tolerate thermal cycling during soft bake without cracking. For this application TSMR-5000 is dispensed over Ti/Au seed layers on GaN-on-sapphire wafers as a single-component resist; the point-of-use ratio is 100% as-received material, and PGMEA addition is limited to 3 vol% only for coater cup rinse recovery to avoid viscosity loss on 150 mm sapphire substrates. The compliance framework includes RoHS 2011/65/EU Annex II restrictions on the final LED chip metallization, IEC 62471:2010 photobiological safety classification for finished LED packages, and SEMI S2-0720 for resist track and exposure equipment safety. The production process uses HMDS priming at 110–130°C, spin coating to 4–10 µm, soft bake at 100–120°C with ramp rate ≤ 15°C/min to avoid sapphire thermal shock, i-line exposure at 365 nm, post-exposure bake, development in 2.38 wt% TMAH, oxygen descum, and electroplating of Cr/Ni/Au or Cu/Ni/Au pads at 0.5–2.0 A/dm². Terminal components are high-brightness LED dies, flip-chip LEDs, and mini-LED transfer-ready chips. The main operational boundary is resist adhesion loss on p-GaN surfaces where residual native oxide persists; a dilute HCl surface pretreatment of 1:10 HCl:H₂O for 30 s before HMDS is used, but overbaking HMDS above 180°C causes scum formation at the resist adjacency zone.
Patterned mesa etching of AlGaN/GaN heterostructures in LED and high-electron-mobility transistor wafer processing uses TSMR-5000 as an etch mask against chlorine-based ICP plasmas. The material is used as a ready-to-spin single-component resist; no fab-side compounding is performed, and if viscosity adjustment is unavoidable due to long idle time, PGMEA is added at ≤2 vol% because greater dilution increases the etch erosion rate under Cl₂/BCl₃ bombardment. Compliance is anchored to SEMI S2-0720 for ICP etcher integration, ISO 14644-1:2015 Class 5 for lithography area particulate control, and RoHS 2011/65/EU Annex II final-device restricted substance screening. The downstream process includes HMDS priming, spin coating to 5–15 µm, soft bake at 100–120°C, near-UV broadband or 365 nm aligner exposure, post-exposure bake at 110–125°C, TMAH development, oxygen descum, and chlorine-based ICP mesa etching with 13.56 MHz RF bias. Terminal output comprises AlGaN/GaN LED wafers with defined isolation mesas, as well as GaN HEMT wafers for RF power amplification and power conversion. The critical boundary condition is the post-plasma strip residue; hard baking above 130°C before etch is avoided because novolac crosslinking then produces carbon-rich residues that adhere to the mesa sidewall and require extended downstream ashing above 80°C to remove.
MEMS accelerometer and gyroscope cavity definition uses TSMR-5000 over severe topographies where the resist film must bridge 5–20 µm deep cavities while maintaining enough thickness over the cavity rim to survive deep reactive ion etching. The resist is applied as a 100% as-supplied single-component material; because no hardener or co-reactant is added, the use ratio remains 100% resist with PGMEA only for coater purge recovery at ≤3 vol%, and multiple coating passes are used to reach 20 µm total thickness with an inter-pass soft bake at 110°C for 60 s. Compliance is reviewed under RoHS 2011/65/EU Annex II for final MEMS package materials, REACH EC 1907/2006 for process chemical risk management, and AEC-Q100 at device level only where the MEMS sensor is qualified for automotive operating conditions. The downstream process includes HMDS priming, first and second spin coating passes, soft bake, 365 nm contact or proximity exposure, post-exposure bake at 110–125°C, development in 2.38 wt% TMAH with intermittent puddle agitation, oxygen descum, and silicon DRIE or buffered oxide etch to define the sacrificial cavity. Terminal component types are capacitive inertial sensors for automotive stability systems, consumer motion units, and pressure sensors. A defined operational limit is relative humidity: processing above 60% RH without pre-coat wafer dehydration causes novolac film swelling and local CD drift exceeding 1.0 µm on 200 mm wafers, so wafers are baked at 110°C for 60 s immediately before coating.
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| Process step | Parameter | Set point or range | Measurement method |
|---|---|---|---|
| Substrate dehydration | Hotplate | 150°C for 60 s | Contact angle or visual inspection |
| Adhesion promotion | HMDS vapor prime | 110°C for 60 s | Contact angle 65–75° |
| Coating | Static dispense | 3–5 mL; spin 800–3,000 rpm | Stylus profilometry after softbake |
| Softbake | Hotplate | 110°C for 120–180 s | Residual solvent ≤3 wt% by ASTM D2369 |
| Exposure | i-line stepper or aligner | 150–250 mJ/cm² at 365 nm | NIST-traceable radiometer |
| Post-exposure bake | Hotplate | 110°C for 60 s | Thermal profile calibration |
| Development | Spray or puddle | 2.38 wt% TMAH, 60–120 s at 23°C | Endpoint by laser interferometry |
| Hardbake | Convection oven | 120–150°C for 30 min | Sidewall profile by SEM cross-section |
| Parameter | TSMR-5000 | Low-viscosity i-line resist | Chemically amplified thick resist | Method |
|---|---|---|---|---|
| Kinematic viscosity at 25°C | 5,000 mPa·s | 10–50 mPa·s | 200–2,000 mPa·s | ASTM D4287 |
| Single-coat film thickness | 8–20 µm | 0.5–3 µm | 10–100 µm | Stylus profilometry |
| Resolution at nominal thickness | 5 µm at 15 µm | 0.5 µm at 1 µm | 2–3 µm at 15 µm | SEM cross-section |
| Post-exposure delay CD shift at 24 h | ≤5% | ≤5% | ≥15% | SEM linewidth metrology |
| Stripping after plating | Solvent or NMP plus O2 plasma | Solvent or NMP plus O2 plasma | Strong acid or piranha plus proprietary solvent | XPS residue analysis |