In 200 mm mixed-signal wafer fabs running 0.35 µm to 0.18 µm process nodes, i-line photoresist is assigned to implant masks, pad oxide etch, and non-critical metal interconnects where 365 nm exposure provides adequate process latitude. When configured for front-end implant masking, THMR-IPS100 is targeted to 1.0 µm to 1.6 µm film thickness on silicon wafers and spin-coated on a TEL ACT-8 or equivalent coater/developer track following a 90°C to 110°C HMDS vapor prime. Softbake is performed at 90°C to 100°C for 60 s to 90 s on a proximity hotplate with ±1°C thermal uniformity across the plate. Exposure on an i-line stepper—typically a Nikon NSR-i12 or ASML PAS 5500/100 class system with 0.45 NA to 0.60 NA—uses 80 mJ/cm² to 150 mJ/cm² open-frame dose at 365 nm. Post-exposure bake is held at 110°C to 120°C for 60 s; thermal drift above ±2°C is generally outside process capability because the photoactive compound diffusion length changes and dense-feature critical dimension can shift by more than 10 nm per degree. Development uses 2.38% tetramethylammonium hydroxide in a double puddle dispense on the coater track, followed by deionized water rinse and spin dry. The exact PAC loading and solvent ratio are not publicly disclosed; lot-specific spin curves and viscosity data must be obtained from the manufacturer certificate of analysis. Compliance for front-end fabs includes SEMI S2 and SEMI S8 equipment safety requirements, cleanroom particle limits under ISO 14644-1 Class 4, and chemical inventory control under REACH Article 33. Terminal products are mixed-signal microcontrollers, power-management ICs, and analogue sensor interfaces.

Power discrete electroplating molds for copper and nickel terminal structures

In power MOSFET and IGBT fabrication, thick resist is required as a plating mask for copper or nickel contact metallization on 150 mm or 200 mm wafers. THMR-IPS100 is coated to 5 µm to 10 µm by reducing spin speed to 1,000 rpm to 2,000 rpm and using a two-step coating program with edge bead rinse; without edge bead removal, accumulated bead height above 20 µm creates mask aligner contact problems. Softbake for thick films is executed at 95°C to 105°C for 120 s to 180 s because thick resist retains solvent at the silicon interface and residual solvent above 3% by mass causes plating bath delamination. Exposure on a broadband mask aligner or i-line stepper requires 150 mJ/cm² to 300 mJ/cm² at 365 nm, with focus offset adjusted toward the top third of the resist film. Development is performed with 2.38% TMAH in multiple puddles of 60 s to 90 s, with spin-rinse between puddles to clear scum from trenches having aspect ratios up to 1.5:1. The electroplating bath for copper terminal structures contains 200 g/L to 220 g/L copper sulfate pentahydrate, 50 g/L to 60 g/L sulfuric acid, and chloride ion at 40 ppm to 60 ppm; brightener concentration is maintained at 0.5 mL/L to 1.5 mL/L depending on feature density and bath age. Plating thickness is typically 5 µm to 15 µm copper, followed by nickel or silver deposition for wire bonding. The resist must withstand the acidic plating bath at 25°C to 35°C for 30 min to 120 min without lifting, swelling, or cracking; post-develop hard bake at 120°C to 130°C for 120 s improves adhesion. Compliance is driven by automotive discrete qualification under AEC-Q101, manufacturing quality under IATF 16949, and wire bond pull measured per MIL-STD-883 Method 2011. Terminal products include power modules for motor drives, DC-DC converters, and automotive traction inverters.

Why does positive i-line resist lose adhesion in 6:1 BOE immersion etching?

The loss of adhesion in buffered oxide etch immersion is not primarily a bulk dissolution event but an interfacial transport failure. In 6:1 buffered HF—prepared from 40% ammonium fluoride and 49% hydrofluoric acid at 6:1 volume ratio—fluoride species migrate through the resist film and attack silicon dioxide or sacrificial glass. If the resist contains residual solvent above 3% by mass or if HMDS vapor prime coverage is incomplete, local etch rate at the interface can exceed 200 nm/min and undercut the resist line mechanically. For MEMS sacrificial oxide or glass etching, THMR-IPS100 is coated at 1.4 µm to 2.2 µm thickness on SOI or borosilicate glass wafers; softbake is 90°C to 100°C for 90 s, and post-develop hard bake at 120°C to 125°C for 120 s densifies the resist surface. Exposure dose is increased to 120 mJ/cm² to 180 mJ/cm² to maintain clearance in 2 µm to 10 µm trenches without over-darkening the resist. Development in 2.38% TMAH is followed by deionized water rinse and spin dry. BOE immersion is carried out at 23°C ± 1°C with mild agitation, and the etch is stopped before visible edge lifting occurs. Compliance for MEMS microfluidic devices includes ISO 13485 for medical components and outgassing screening per ASTM E595-15 for cavity packages. Terminal products are inertial sensors, pressure transducers, and microfluidic chips.

When via diameters shrink below 10 µm in redistribution layer and copper pillar bumping processes, the limiting factor is no longer optical resolution but sidewall integrity during electroplating. THMR-IPS100 is used as a plating mask at 8 µm to 15 µm thickness on 200 mm wafers with a two-coat process; the first coat is softbaked at 95°C for 90 s and the second at 100°C for 180 s to remove solvent in the thicker film. A proximity mask aligner with 365 nm broadband output delivers 200 mJ/cm² to 400 mJ/cm²; exposure is split into two passes at different focus offsets to reduce undercut and improve sidewall angle. Development with 2.38% TMAH uses a low-pressure spray mode for the first 30 s followed by static puddle for 60 s to clear scum in 10 µm to 20 µm vias. The copper plating bath for redistribution lines contains 55 g/L to 65 g/L copper ions, 10 g/L to 15 g/L sulfuric acid, and a carrier/brightener system maintained within the supplier analytical control limits. A plating height of 5 µm to 12 µm is typical for redistribution conductors, while copper pillar bumping uses 20 µm to 40 µm total copper height; for pillar heights above 25 µm, dry-film resist is generally preferred because spin-on resist thickness uniformity degrades above 15 µm. Published data for this specific configuration of THMR-IPS100 in copper pillar bumping is limited, and process qualification must be performed with the actual plating chemistry. Compliance for wafer-level packaging includes JEDEC JESD22-A104 thermal cycling at package level and IPC/JEDEC J-STD-020 moisture sensitivity classification for final assembly. Terminal products are fan-in WLCSP, power management modules, and RF front-end modules.

If SAW filter aluminium electrodes require sub-micrometre wet etch linewidths

Surface acoustic wave filter electrode patterning uses thin i-line resist to define aluminium or aluminium-copper interdigital transducers with linewidths from 0.4 µm to 1.2 µm on lithium tantalate or quartz substrates. Because wet etching of aluminium is isotropic, the resist is coated at 0.5 µm to 0.9 µm to minimize absolute bias loss; spin speed is set between 3,000 rpm and 5,000 rpm. Softbake at 85°C to 95°C for 60 s reduces solvent from the thin film without excessive hardening that would retard development at sub-micrometre openings. Exposure is performed at 365 nm on a stepper capable of 0.50 NA to 0.63 NA with dose from 60 mJ/cm² to 120 mJ/cm²; overexposure must be avoided because aluminium wet etch bias can exceed 0.3 µm per edge. The developer is 2.38% TMAH at 23°C with a single puddle of 45 s to 60 s, followed by post-develop hard bake at 110°C to 120°C for 60 s. The aluminium etchant is a phosphoric acid/acetic acid/nitric acid mixture; a typical ratio is 16:1:1:2 for H3PO4:HNO3:CH3COOH:H2O, with temperature controlled at 40°C to 45°C. The resist must withstand this acidic mixture for 2 min to 5 min without lifting or undercutting. Compliance is driven by final component requirements under RoHS 2011/65/EU Annex III exemptions relevant to piezoelectric ceramics and by end-device RF performance standards in the IEC 62604 family. Terminal products are RF filters and duplexers for smartphones and IoT nodes.

Applying lift-off resists in GaN photonic and LED electrode formation

Metal lift-off in GaN-based LED and photonic device fabrication requires a resist profile that prevents continuous metal sidewall coverage. Standard positive i-line resists produce a trapezoidal profile, whereas lift-off demands a re-entrant or negative profile. THMR-IPS100 can function in lift-off if processed with a post-exposure ammonia image-reversal cycle or a chlorobenzene soak that selectively inhibits the top surface of the resist. The resist is coated at 1.2 µm to 2.5 µm on sapphire or GaN-on-silicon wafers, softbaked at 90°C to 100°C for 90 s, exposed at 365 nm with 80 mJ/cm² to 140 mJ/cm², then treated with chlorobenzene for 5 min to 10 min before development in 2.38% TMAH. The resulting overhang allows deposition of 5 nm to 20 nm of titanium or chromium as an adhesion layer and 150 nm to 500 nm of gold or platinum as the electrode metal without sidewall bridging. Published data for this specific configuration of THMR-IPS100 in chlorobenzene lift-off is limited, and the process window must be validated by cross-sectional SEM. Stripping is performed in N-methyl-2-pyrrolidone or an amine-based stripper at 70°C to 85°C for 20 min to 40 min, with ultrasonic agitation restricted to avoid damaging the GaN surface. Compliance for LED fabrication includes final product exemptions under RoHS 2011/65/EU and electrostatic discharge control per ANSI/ESD S20.20. Terminal products are high-power LEDs, micro-LED arrays, and photonic integrated circuits.

In thin-film magnetic head and sensor manufacturing, the useful application envelope of i-line resist is confined to air-bearing surface patterning, lapping guides, and electroplated coil structures where linewidths remain above 0.8 µm. The resist is spun to 1.0 µm to 3.5 µm on ceramic AlTiC wafers; softbake is 90°C for 90 s, exposure is 100 mJ/cm² to 180 mJ/cm² at 365 nm, and development is performed in 2.38% TMAH. For electroplated coil structures, the copper plating bath is operated at 25°C to 30°C with 30 min to 60 min plating time, producing 1.0 µm to 5.0 µm of copper. The main process conflict is substrate reflectivity: AlTiC is rougher and less reflective than silicon, so dose uniformity is evaluated by scanning electron microscope measurement of resist feature width across the wafer. Compliance for magnetic heads includes ISO 14001 environmental management in the fab and customer-specific cleanroom particle limits under ISO 14644-1 Class 5. Terminal products are hard disk drive read-write heads and magnetic sensors.