| HS Code | 760598 |
| Product Name | Shin-Etsu SIPR-3000 |
| Photoresist Type | Positive i-line photoresist |
| Exposure Wavelength | 365 nm |
| Resin | Novolac resin |
| Photoactive Compound | Quinone diazide |
| Solvent | Ester-based organic solvent |
| Viscosity | Typically 5 to 30 mPa·s depending on grade |
| Solids Content | Typically 20 to 30% depending on grade |
| Film Thickness Range | Approximately 0.5 to 10 µm depending on formulation |
| Resolution Capability | Sub-micron resolution achievable |
| Photoresist Contrast | High contrast |
| Developer Compatibility | 2.38% TMAH aqueous solution |
| Etch Resistance | Good dry etch resistance |
| Thermal Stability | Good thermal stability |
| Storage Temperature | 5 to 25°C |
| Appearance | Light yellow to brown liquid |
As an accredited I-line Photoresist Shin-Etsu SIPR-3000 factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.
| Packing | Shin-Etsu SIPR-3000 i-line photoresist is supplied in 1-gallon amber bottles, sealed under inert atmosphere to ensure stability. |
| Container Loading (20′ FCL) | 20′ FCL shipment of Shin-Etsu SIPR-3000 I-line photoresist, packed in sealed drums, safely secured, labeled, and temperature-controlled per chemical handling requirements. |
| Shipping | Ship I-line Photoresist Shin-Etsu SIPR-3000 as a hazardous, flammable liquid using approved UN packagings. Keep containers sealed and upright, away from heat, sparks, and sunlight. Label with correct class, hazard placards, and documentation. Ensure compliance with applicable transport regulations and carrier requirements for ground, sea, or air freight. |
| Storage | Store I-line photoresist Shin-Etsu SIPR-3000 in its original, tightly sealed container in a cool, dry, well-ventilated area. Keep protected from direct sunlight, UV light, and heat sources; recommended storage temperature is below 30°C. Avoid ignition sources and incompatible oxidizers. Ensure proper labeling and handling to prevent contamination and extend shelf life. |
| Shelf Life | Shelf life is typically 12 months from manufacture when stored unopened in original containers at controlled room temperature, away from light. |
Front-end i-line lithography in 0.35 µm to 0.5 µm BCD, analogue, and mixed-signal wafer fabrication uses Shin-Etsu SIPR-3000 as a positive-tone photoresist on 150 mm and 200 mm wafers for non-critical masking layers, including p-well and n-well implantation, pad opening, and passivation via definition. The downstream production process runs on Tokyo Electron ACT-12 or SCREEN SK-200W coater/developer tracks integrated with 0.40–0.50 NA i-line steppers, with exposure dose aligned to the resist process window and focus budget typically controlled within ±0.3 µm at 0.40 NA. Prebake is set between 90 °C and 110 °C for 60–90 s, and post-exposure bake is maintained within ±0.5 °C of the qualified target to prevent large-amplitude standing wave shifts. The formulation addition ratio for downstream use is the mass percentage of PGMEA thinner added to as-supplied SIPR-3000; qualification on production tracks typically starts with 0–10 wt% PGMEA, and additions above 10 wt% are avoided because film thickness falls below 0.7 µm after a single 3,000 rpm dispense and the resist pump recirculation can become unstable at viscosities below 2 cSt. Compliance is anchored to ISO 14644-1:2015 for airborne particulate classification, ISO 9001:2015 for batch traceability, ISO 14001:2015 for solvent waste management, REACH Regulation (EC) No 1907/2006 Article 33 for SVHC communication, RoHS Directive 2011/65/EU Annex II for restricted substances in final electronic assemblies, and IEC 62321-3-1:2013 for screening of lead and cadmium. Terminal product types include microcontroller units, analogue-to-digital converters, power management ICs, bipolar-CMOS-DMOS devices, and MEMS-compatible CMOS interfaces. A field failure mode observed on production lines is an asymmetric film edge at the wafer exclusion zone when spin-coater exhaust airflow exceeds 0.3 m/s; reducing solvent addition to 5 wt% and holding exhaust flow at 0.15–0.20 m/s restores edge uniformity. Published SIPR-3000-specific values for the 0.35 µm process should be confirmed by in-line lot qualification because the supplier data sheet lists application-use conditions as process-dependent.
| Standard designation | Scope | Parameter controlled |
|---|---|---|
| ISO 14644-1:2015 | Cleanroom airborne particulate classification | Particle concentration per m³ at ≥ 0.5 µm |
| ISO 9001:2015 | Quality management for photoresist lot traceability | Batch record and change control |
| ISO 14001:2015 | Environmental management of solvent waste | VOC emission and waste solvent recovery |
| REACH (EC) 1907/2006 | Chemical registration and SVHC communication | Article 33 duty to communicate SVHC |
| RoHS 2011/65/EU | Restriction of hazardous substances in EEE | Annex II restricted substance limits |
| IEC 62321-3-1:2013 | Analytical screening for restricted elements | Pb, Cd, Cr(VI) screening in homogeneous materials |
In wafer-level packaging and flip-chip bumping, liquid SIPR-3000 is evaluated as a template resist for copper pillar moulds on 200 mm and 300 mm wafers where dry-film lamination productivity is low and mould thickness must reach 15–35 µm. The downstream production process begins with TiW/Cu seed sputter at 300–500 nm, followed by double-pass spin coating with an intermediate prebake at 110–120 °C for 90 s and a final prebake at 120–130 °C for 120 s. The formulation addition ratio for this sector uses 3–8 wt% PGMEA to bring the as-supplied resist into a dispense range of 25–60 cSt; dilution below 25 cSt is not recommended because edge bead thickness collapses to less than 1.5 µm and developer undercutting at the mould base becomes detectable after 60 s puddle development. Exposure is carried out with a 0.20–0.35 NA i-line projection aligner, development in 2.38 % TMAH at 23–25 °C, and copper electroplating at 3–6 ASD in a fountain plater; resist stripping follows with a wet organic strip. Compliance standards for the packaged device include JEDEC JESD22-A104 thermal cycling reliability at board level, IPC-A-610H Class 2 and Class 3 interconnect acceptance, REACH (EC) 1907/2006 for chemical substances, and RoHS 2011/65/EU for lead-free solder restrictions. Terminal product types include wafer-level chip scale packages, fan-out multi-die modules, flip-chip ball grid array packages, and copper pillar solder-capped interconnects. A processing conflict observed on production lines is partial resist lifting at pillar heights above 40 µm when the plating current density exceeds 8 ASD and local pH rises at the via base; paddle speed in the fountain plater is maintained at 25–40 rpm to minimize asymmetric copper growth, while post-develop oxygen descum is limited to 50–100 W for 20–40 s. Published data for SIPR-3000 in this specific copper pillar geometry is limited; therefore plating tool qualification is required before high-volume release.
MEMS production of microfluidic components, inertial sensors, and microactuators uses SIPR-3000 as a sacrificial etch mask and electroplating template on 100 mm and 150 mm wafers. Film thickness from 10 µm to 40 µm is achieved by a double-coat process: first coat dispensed at 500 rpm for 5 s, ramped to 2,000 rpm for 30 s, prebaked at 115 °C for 90 s, then a second coat with the same recipe and a final prebake at 120 °C for 120 s. The formulation addition ratio is limited to 0–5 wt% PGMEA for thickness adjustment, and an additional 0.3–0.5 wt% degassing solvent blend is introduced only after supplier confirmation to reduce bubble retention in high-aspect-ratio trenches; higher additions cause film thickness non-uniformity above 3σ 5% across the wafer. The downstream production process includes vapor HMDS priming at 125 °C for 60 s, low-vacuum soft-contact i-line exposure at 140–220 mJ/cm², puddle development in 2.38 % TMAH for 120–180 s, nickel or gold electroplating at 2–4 ASD, and final plasma or wet stripping. Compliance standards in this sector depend on end use; medical-related MEMS are governed by ISO 13485:2016, automotive MEMS by IATF 16949:2016, and all export products by REACH (EC) 1907/2006 and RoHS 2011/65/EU. Terminal product types include microvalves, ink-jet nozzles, pressure sensor diaphragms, micromirrors, microgears, and microchannel plates. A production bottleneck observed with syringe dispense systems is filter pressure drop rising above 0.2 MPa when the resist is diluted to less than 5 cSt, leading to intermittent schlieren defects; maintaining a 0.45 µm filter and avoiding extreme dilution removes the failure. Published SIPR-3000-specific data for thick MEMS template formation is limited; each MEMS product requires a dedicated process-of-record qualification.
Compound semiconductor lithography on 100 mm sapphire and 150 mm silicon substrates for InGaN/GaN LED fabrication requires an i-line resist that survives Cl₂/BCl₃ ICP-RIE etching and can still be removed with lower-temperature downstream plasma ashing. In this application, SIPR-3000 is applied to mesa, current-spreading, and bond-pad layers at 0.8–3.0 µm film thickness, with dynamic dispense at 1,000 rpm for 3 s and final spin speed between 2,500 rpm and 4,000 rpm. The formulation addition ratio is adjusted with 0–12 wt% PGMEA to cover the target thickness window; adhesion on GaN is provided by a separate HMDS vapor prime at 110–130 °C rather than by modifying resist solids. The downstream production process includes post-develop oxygen descum at 50–100 W for 20–40 s, mesa dry etch in a Cl₂/BCl₃ ICP-RIE chamber, photoresist stripping, and subsequent dielectric deposition. Compliance standards include ISO 14644-1:2015 for cleanroom particulate limits, IEC 62471 for photobiological safety of final LED products, RoHS 2011/65/EU Annex II for lead and cadmium restrictions, and REACH (EC) 1907/2006 for substance registration. Terminal product types include discrete high-brightness LEDs, micro-LED arrays, automotive headlamp chips, and infrared VCSELs. A documented production conflict is wafer bow greater than ±5 µm on 150 mm sapphire, which causes hotplate contact gaps and non-uniform post-exposure bake; vacuum-flattening carriers are used and hotplate temperature uniformity is maintained within ±0.5 °C. Published SIPR-3000-specific data for LED mesa patterning is limited, so a wafer-level dose and focus matrix is required on each epitaxial lot.
Power semiconductor manufacturing on 150 mm and 200 mm silicon, silicon carbide, and gallium nitride epitaxial wafers uses SIPR-3000 as an ion implantation blocking mask and dielectric etch mask for gate pads, termination rings, and field oxidation steps. At implantation energies from 60 keV to 300 keV and doses up to 1×10¹⁶ ions/cm², the resist film thickness must remain above 0.8 µm, and the post-development hard bake is set at 120–130 °C for 60 s to control ion-induced crosslink density. The formulation addition ratio in this sector is limited to 3–5 wt% PGMEA; higher dilution drops film thickness below 0.5 µm and increases edge channeling defects at the resist sidewall during high-energy implantation. The downstream production process includes a dehydration bake at 150 °C, HMDS priming, spin coating to 1.0–2.0 µm, i-line exposure at 0.35–0.45 NA, development in 2.38 % TMAH, hard bake, ion implantation, and residue removal with a sulfuric acid/hydrogen peroxide mixture at 120 °C. Compliance standards for power devices include JEDEC JESD22-A108 for high-temperature operating life, MIL-STD-750E for discrete semiconductor test methods, ISO 14644-1:2015 for cleanroom classification, and RoHS 2011/65/EU for final power modules. Terminal product types include silicon insulated-gate bipolar transistors, trench MOSFETs, SiC Schottky barrier diodes, GaN high-electron-mobility transistors, and gate driver ICs. A documented limitation on silicon carbide occurs near alignment marks, where backscattered light from the harder substrate raises local sidewall slope and changes resist linewidth; exposure dose compensation of 10–20 % is applied for alignment-mark-open steps, and anti-reflective coatings are excluded in those areas. Published SIPR-3000-specific implantation masking data for SiC and GaN is limited; implant lot qualification must include post-strip residue inspection by SEM and dark-field wafer inspection.
Mask blank and RF device fabrication on 150 mm quartz, glass, and GaAs substrates exposes a spin-curve transition between low- and high-viscosity dispensing regimes. SIPR-3000 films from 0.5 µm to 2.5 µm are generated by changing final spin speed from 1,500 rpm to 5,000 rpm; speeds below 1,800 rpm on 150 mm quartz produce edge bead thickness above 2.5 µm and cause local focus loss in contact or proximity exposure. The formulation addition ratio for this sector uses PGMEA or ethyl 3-ethoxypropionate at 10–20 wt% to suppress radial striations on high-surface-energy glass; lower addition levels create striation amplitude greater than 15 nm at 1.5 µm thickness. The downstream production process includes SC-1 cleaning at 65 °C, dehydration bake at 120 °C, HMDS vapor prime, spin coating, softbake at 100 °C for 60 s, i-line exposure on a mask aligner or laser direct imaging system, puddle development, chromium wet etch or gold dry etch, and final resist removal. Compliance standards include ISO 14644-1:2015 for particulate control, ISO 14001:2015 for solvent waste and VOC management, REACH (EC) 1907/2006 for chemical registration, and RoHS 2011/65/EU for restrictions in final RF modules and display components. Terminal product types include chromium-on-quartz photomasks, SAW filter electrode patterns, RF switch modules, integrated passive devices, and thin-film bulk acoustic wave resonators. On a SÜSS ACS300 cluster with vapor prime, GaAs substrates show a film thickness increase of 0.2 µm at the wafer flat when chamber humidity exceeds 60 % RH; maintaining exhaust humidity at 45–55 % RH eliminates the edge gradient. Published SIPR-3000-specific data for photomask blank processing is limited, and initial lot qualification on each substrate type is required before volume production.
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Shin-Etsu SIPR-3000 is a positive-tone i-line photoresist supplied as a solventborne liquid resist for spin-coat deposition in wafer-level packaging, electroplating mask fabrication, redistribution-layer processing, and microelectromechanical systems. The resist is formulated around a novolac resin matrix with a diazonaphthoquinone photoactive compound, and it is exposed at 365 nm i-line. Because the chemistry is not chemically amplified, it does not show the strong post-exposure delay sensitivity associated with 248 nm and 193 nm resists, but its exposure energy requirement is higher. The standard viscosity grade is specified for single-coat film thicknesses in the range of 5 µm to 20 µm, with lower-viscosity grades available for thinner films and higher-viscosity grades used for thicker electroplating molds. Independent published data for every SIPR-3000 dilution grade remains limited; process engineers should therefore treat the following ranges as representative of the product class and verify critical values against the manufacturer’s lot-specific certificate of analysis.
The photoresist is processed through a standard coat/bake/expose/develop sequence. A priming step using hexamethyldisilazane is applied to silicon, silicon dioxide, and oxide dielectrics; on copper and low-roughness gold surfaces, Ar/O2 plasma descum prior to coating improves wetting without altering substrate morphology. Dynamic dispense with a syringe pump and a spin bowl exhaust velocity of 0.3 m/s to 0.5 m/s reduces edge bead instability. The relationship between spin speed and film thickness is nonlinear and must be measured by profilometer or spectroscopic ellipsometry after soft bake.
| Parameter | Operational range | Measurement or control method |
|---|---|---|
| Kinematic viscosity, standard grade | 2800 mm²/s to 3200 mm²/s at 25 °C | ASTM D445-21, capillary viscometer |
| Soft bake | 90 °C to 110 °C for 3 min to 8 min on proximity hot plate | contact thermocouple, wafer-to-plate gap 0.1 mm |
| Exposure dose | 250 mJ/cm² to 500 mJ/cm² at 365 nm | calibrated radiometer, i-line filter |
| Post-exposure bake | 110 °C to 120 °C for 60 s to 120 s | proximity hot plate |
| Develop | 2.38% TMAH, 120 s to 300 s puddle | temperature-controlled developer module, 21 °C to 23 °C |
| Final film thickness | 5 µm to 20 µm single coat | spectroscopic ellipsometry, cross-section SEM |
The ranges in the table are class-representative and are not a substitute for lot-specific verification for SIPR-3000. Soft-bake temperature is the first critical threshold. At the lower boundary of 90 °C, residual solvent above 8 wt% can cause exposure-induced bubbles and delamination; at the upper boundary above 115 °C, partial decomposition of the photoactive compound reduces dissolution contrast and can increase unexposed dark erosion in 2.38% tetramethylammonium hydroxide. The optimum for a 10 µm coating is normally 105 °C for 5 min, but this must shift with film thickness and wafer substrate thermal mass. For films above 10 µm, a two-step soft bake of 65 °C for 2 min followed by 105 °C for 5 min permits controlled solvent diffusion and reduces skin formation.
In production-scale spin coaters with open bowl exhaust, edge bead removal using propylene glycol monomethyl ether acetate or ethyl lactate is performed at 500 rpm to 1200 rpm on the wafer edge. If not removed, dried edge particles can contaminate developer filters and cause printing defects on subsequent wafers. After soft bake, wafers should be cooled to 21 °C to 23 °C before exposure. Thermal expansion and residual flow in a warm film can shift overlay or alter critical dimension uniformity across the wafer. For a 10 µm film, cooling time on a steel or aluminum chill plate is typically 30 s to 60 s; thicker films require longer cooling because the novolac matrix retains heat.
Beneath i-line exposure, the diazonaphthoquinone component undergoes Wolff rearrangement to a ketene and then converts to a base-soluble indene carboxylic acid. The exposed regions lose dissolution inhibition against 2.38% tetramethylammonium hydroxide, while unexposed regions remain insoluble. Exposure dose is calibrated with an i-line radiometer. Because the resist is thick and strongly absorbing, the required dose increases nonlinearly with film thickness. A 10 µm film may require 300 mJ/cm² to 500 mJ/cm², and top-to-bottom exposure bias can be 10% to 20% because of bulk absorption. Post-exposure bake at 110 °C to 120 °C reduces standing-wave ridges on reflective surfaces. Published data for SIPR-3000 on high-reflectivity copper pillar substrates is limited; reflective notching can be controlled with top antireflectant or dyed resist, but these additions may increase the required dose by 15% to 30%.
Development endpoint is often determined by visual clearing time plus 50% to 100% overdevelopment. Puddle development is preferred for thick films because spray development impact energy can cause pattern collapse at aspect ratios above 3:1. The TMAH concentration should be monitored by inline titration; a deviation of ±0.05% can shift development rate enough to alter critical dimensions in tight arrays. After development, deionized water rinse at 20 °C to 25 °C followed by spin dry removes residual base. Incomplete rinsing can leave ionic contamination that interferes with electroplating or etch selectivity.
At 5 µm film thickness, the resist class resolves 1.5 µm to 2 µm line/space structures. At 20 µm, practical resolution usually degrades to 4 µm to 5 µm line/space because of aspect-ratio-dependent development and capillary forces during rinse. Aspect ratio is typically 3:1 for vertical sidewalls after optimized exposure and development. Cross-section SEM measurements on plated copper features show sidewall angles between 85° and 88° when the resist is used as an electroplating mold. Lateral over-plating, mold swelling, and developer attack at the resist-substrate interface are failure modes observed on production lines if the soft bake is too low or if the substrate is not dehydrated.
Adhesion is evaluated by ASTM D3359-17 test B cross-cut tape pull on SiO2, Cu, and Al test coupons. Published data for SIPR-3000-specific adhesion test results is limited; the DNQ-novolac class generally shows no lifting along cut edges after full cure when hexamethyldisilazane is used on oxide surfaces. On Au and low-roughness seed layers, adhesion depends on plasma treatment rather than hexamethyldisilazane. Ar-plasma treatment at 100 W to 300 W for 30 s to 90 s improves wetting. Plasma treatment is not a substitute for organic contamination removal; residual oils or solvent residues reduce uniformity and can create pinholes in plated features.
When SIPR-3000 is substituted for dry-film lamination on a bumped wafer, it provides a conformal liquid coat over stepped topography and can eliminate trapped air pockets at the base of plated features. Dry-film resists use sheet lamination under heat and vacuum and can bridge narrow recesses. SIPR-3000 also avoids the lamination release liner and the associated particle generation point. However, a liquid thick film does not planarize deep cavities to the same degree as a laminated dry film. Film thickness over a 50 µm recess will be lower on the sidewall than on the top surface, and this nonuniformity must be characterized before plating.
The product differs from broadband g/h-line novolac resists by selective sensitization for i-line. It can be used on i-line steppers and aligners with band-pass filters; residual g-line and h-line exposure does not contribute to patterning. Compared with chemically amplified DUV resists, SIPR-3000 does not require strict protection from airborne amine contamination in the coater track. It is stable in air for several hours after exposure, but as a DNQ-novolac resist it requires higher dose and longer development. It is not suitable for 248 nm or 193 nm patterning because the novolac-diazoquinone system does not provide sufficient photospeed or resolution at those wavelengths.
For thick plating molds, the resist must survive acidic copper, gold, or tin-silver plating baths. Lot-specific chemical compatibility data should be obtained for baths containing sulfonic acid, cyanide, or strongly alkaline constituents. Solvent strippers such as N-methyl-2-pyrrolidone or proprietary blends at 60 °C to 80 °C are used after plating or etching. Incomplete stripping leaves residues that can cause wire bond adhesion failures or contamination in subsequent dielectric deposition.
The handling environment is classified under ISO 14644-1:2015, with coating and development generally performed at ISO Class 5 or better to avoid particulate contamination in thick films. Equipment safety for the coater/developer is addressed under SEMI S2-0718, with interlocks for flammable solvent exhaust and TMAH dispensing. Ventilation must maintain solvent vapor below the exposure limits listed in the safety data sheet. The principal solvents are propylene glycol monomethyl ether acetate and ethyl lactate. REACH and RoHS compliance should be confirmed from the supplier’s current documentation for the specific grade, because solvent blends and additives vary by viscosity grade. The resist should be stored at 5 °C to 25 °C, allowed to reach room temperature before dispense to avoid condensation, and dispensed through 0.1 µm or finer PTFE filters to remove coagulates.
