High thermal conductivity epoxy molding compound (EMC) Electronic/EL grade, designated HTC-EMC-EL 9620, is a transfer-molding thermoset formulated for encapsulation of power discrete packages, power modules, and LED lead-frame devices where heat transfer through the molding layer is a design constraint. The matrix consists of a biphenyl epoxy resin, a phenol-novolac hardener, an imidazole-type cure catalyst, and a multimodal filler network of spherical alumina, platelet boron nitride, and low-sodium fused silica. Filler content is adjusted so that through-plane thermal conductivity remains in the range 3.0 W/m·K to 5.2 W/m·K when cured plaques are measured by ASTM D5470-17. Cured density is 1.95 g/cm³ to 2.20 g/cm³ by ASTM D792-13. Spiral flow at 175 °C and 6.9 MPa transfer pressure is maintained between 90 cm and 140 cm by ASTM D3123. The Electronic/EL grade is distinguished from conventional semiconductor-grade EMC by hydrolyzable chloride content below 20 ppm, extractable sodium and potassium below 5 ppm each, and aqueous-extract ionic conductivity below 50 µS/cm to reduce electrochemical migration risk under biased humidity testing.
Which Property Set Separates This Grade from Standard Semiconductor Encapsulants?
The property profile is defined by the need to balance thermal conductivity against moldability. Standard semiconductor EMCs typically deliver through-plane thermal conductivity of 0.7 W/m·K to 1.2 W/m·K; the high-conductivity grade replaces part of the fused-silica filler with alumina and boron nitride, increasing thermal conductivity but also raising melt viscosity and reducing spiral flow. A comparative property set is provided in Table 1.
| Property | HTC-EMC-EL 9620 | Standard semiconductor EMC | Low-stress semiconductor EMC | Test method |
|---|---|---|---|---|
| Through-plane thermal conductivity | 3.0–5.2 W/m·K | 0.7–1.2 W/m·K | 0.9–1.5 W/m·K | ASTM D5470-17 |
| Filler loading | 72–85 wt% | 70–80 wt% | 65–75 wt% | ISO 11358-1:2022 |
| Flexural modulus | 18–25 GPa | 15–20 GPa | 8–12 GPa | ASTM D790-17 |
| CTE α1 below Tg | 12–18 ppm/°C | 15–22 ppm/°C | 20–28 ppm/°C | ISO 11359-2:2021 |
| CTE α2 above Tg | 40–60 ppm/°C | 55–80 ppm/°C | 70–100 ppm/°C | ISO 11359-2:2021 |
| Glass transition temperature by DSC | 165–210 °C | 150–190 °C | 130–170 °C | ISO 11357-2:2020 |
| Spiral flow at 175 °C, 6.9 MPa | 90–140 cm | 120–180 cm | 100–160 cm | ASTM D3123 |
| Gel time at 175 °C | 35–70 s | 40–80 s | 45–90 s | ASTM D4473-08 |
| Hydrolyzable chloride | <20 ppm | <50 ppm | <50 ppm | IPC-TM-650 2.3.25 |
| Volume resistivity after 24 h deionized-water immersion | 1 × 10¹⁴ Ω·cm | 1 × 10¹⁴ Ω·cm | 1 × 10¹⁴ Ω·cm | ASTM D257-14 |
The high-conductivity grade has a flexural modulus of 18 GPa to 25 GPa, compared with 8 GPa to 12 GPa for a low-stress semiconductor EMC. This higher modulus is a direct consequence of the platelet and angular filler architecture and is relevant for packages with large die-to-package area ratios. The coefficient of linear thermal expansion below the glass transition temperature is lower, at 12 ppm/°C to 18 ppm/°C, which improves die stress management but increases substrate warpage potential on thin substrates. Above the glass transition, CTE increases to 40 ppm/°C to 60 ppm/°C. Cure conversion after 90 s at 175 °C is typically 85% to 95% by DSC; post-mold cure at 150 °C for 4 h raises conversion above 98%.
When a Power Module Requires Through-Plane Thermal Conductivity Above 4 W/m·K
For a molded power module or discrete package, the EMC layer contributes a thermal resistance proportional to bond-line thickness and inverse proportional to thermal conductivity. With the HTC-EMC-EL 9620-05 variant, through-plane thermal conductivity reaches 4.5 W/m·K to 5.2 W/m·K at 25 °C. At a bond-line thickness of 0.4 mm over a 10 mm × 10 mm die pad, the one-dimensional thermal resistance contribution is approximately 0.08 K/W. At 1.0 mm bond-line thickness, the contribution increases to approximately 0.20 K/W. These values are calculated for one-dimensional conduction without contact resistance and are not package junction-to-case resistance values unless die-attach, leadframe, and interface resistances are included.
In-plane thermal conductivity is deliberately higher due to shear-induced orientation of platelet boron nitride during transfer flow. Laser-flash measurements on 30 mm × 30 mm × 1 mm cured coupons per ASTM E1461-13 show in-plane values of 8 W/m·K to 12 W/m·K, producing a through-plane-to-in-plane anisotropy ratio between 2:1 and 3:1. This anisotropy favors lateral heat spreading in leadframe packages but reduces the effective through-plane conductivity of thick encapsulation layers. For semiconductor applications requiring junction temperatures up to 200 °C, the filler network remains stable; however, published data for this specific configuration is limited above 200 °C, and continuous operation above the glass transition should be avoided due to CTE mismatch and warpage risk.
Processing Limitations and Moisture Sensitivity in the EL Grade
Production-scale transfer molding trials on 80 mm barrel-diameter presses with 120-ton clamp force and 0.5 mm/s to 2.5 mm/s plunger speeds show that filler loading above 72 wt% reduces spiral flow below 85 cm and raises apparent melt viscosity into the 60 Pa·s to 100 Pa·s range at 175 °C. The practical processing window therefore narrows to 170 °C–180 °C mold temperature and 6.0 MPa–8.0 MPa transfer pressure. Below 170 °C, gel time lengthens but viscosity remains high, causing incomplete fill in cavities with vent depths below 25 µm. Above 180 °C, gel time shortens to below 25 s, producing knit lines and incomplete cavity packing. Mold cavities require vacuum venting and wear-resistant tool steel or tungsten carbide surfaces because alumina and boron nitride are abrasive; mold wear rates are approximately 2–3 times those observed with standard silica-filled EMC under identical shot counts.
Wire sweep on 25 µm diameter gold bond wires, measured by X-ray after molding, increased from less than 3% at 75 wt% filler loading to over 7% at 82 wt% filler loading. The mechanism is local filler migration and increased shear at the wire–resin interface. Lot-to-lot spiral flow variance is controlled within ±10 cm; if filler moisture exceeds 0.2 wt%, spiral flow variance expands to ±20 cm and hot hardness after 90 s at 175 °C falls below 75 Shore D. The material is supplied in sealed moisture-barrier bags at -20 °C. After removal from cold storage, tempering in the unopened bag at 25 °C and 55% RH for 12 h is required. Once opened, preforms should be consumed within 24 h; if ambient relative humidity exceeds 60% RH, working time is reduced to 8 h. Thermal pre-drying of pellets is not recommended because it advances B-staging and reduces flow at high filler loading. Compatibility with amine-based surface treatments should be verified before use; amine species can accelerate the cure reaction during storage and alter gel time.
Differences in filler architecture alter both thermal transfer and mechanical stress
The difference from standard semiconductor EMC arises primarily from filler architecture and purity. Standard grades rely on spherical fused silica to maximize flow and reduce equipment wear; their through-plane thermal conductivity rarely exceeds 1.2 W/m·K. The high-conductivity grade substitutes a portion of the silica with alumina to raise bulk conductivity and adds platelet boron nitride to create an in-plane conductive network. Compared with low-stress EMC, which uses a flexibilized resin to achieve flexural modulus of 8 GPa to 12 GPa, the high-conductivity grade maintains 18 GPa to 25 GPa modulus and lower CTE, reducing bulk thermal expansion but increasing transfer-molding stress on large dies. Compared with liquid epoxy potting and adhesive systems, the solid transfer-molding compound has no solvent or mixing step, provides higher glass transition, lower CTE, and higher modulus, and produces a consolidated package with better resistance to popcorning and thermal cycling. However, it is opaque and black, so it cannot replace transparent optical encapsulants. The grade is not recommended for packages requiring a flexural modulus below 10 GPa or for sections thicker than 3 mm where through-plane anisotropy limits effective thermal dissipation.
The Electronic/EL purity grade also differs from industrial structural EMC by limits on total hydrolyzable chloride, alkali-metal extraction, and cure-catalyst residues. Industrial grades may accept chloride above 50 ppm; this grade is controlled below 20 ppm. Low ionic contamination is critical for biased humidity and high-temperature reverse-bias tests where chloride and sodium accelerate aluminum metallization corrosion. The flame-retardant system is available in halogen-free versions with total chlorine below 900 ppm, total bromine below 900 ppm, and combined halogen below 1500 ppm per IEC 61249-2-21.
Compliance verification for the Electronic/EL grade is summarized in Table 2. The values are typical batch-release ranges, not specific lot limits unless stated otherwise.
| Requirement | Value or status | Reference |
|---|---|---|
| RoHS restricted substances | Below maximum concentration values in Annex II: 0.1 wt% for Pb, Hg, Cr(VI), PBB, PBDE; 0.01 wt% for Cd | 2011/65/EU Annex II |
| REACH SVHC | No intentionally added substances above declaration threshold; lot-specific declaration available | Regulation (EC) No 1907/2006 |
| Halogen-free option | Total Br <900 ppm, total Cl <900 ppm, combined <1500 ppm | IEC 61249-2-21 |
| Flammability rating | V-0 at 1.6 mm specimen thickness | UL 94 / IEC 60695-11-10 |
| Extractable ions | Na⁺ <5 ppm, K⁺ <5 ppm, Cl⁻ <20 ppm, aqueous-extract conductivity <50 µS/cm | IPC-TM-650 2.3.25 |
In a silicon-carbide power module encapsulation application, the grade has been transfer-molded over 8 mm × 8 mm die attach with copper clip interconnects at a mold temperature of 175 °C, transfer pressure of 7.0 MPa, and post-mold cure of 4 h at 150 °C. The as-molded packages exhibited no short shots and no wire sweep greater than 5% on 25 µm gold wires. Thermal resistance measurements by JEDEC JESD51-14 transient thermal testing showed a reduction in EMC layer thermal resistance of approximately 50% relative to a standard silica-filled EMC at equivalent thickness, but published data for this specific configuration is limited and package-level results depend on die-attach voiding, leadframe thickness, and interface delamination.