On 200 mm and 300 mm CMOS manufacturing lines, passivation oxide opening over aluminum-copper and aluminum-silicon bond pads is performed with electronic/EL-grade silicon dioxide/aluminum etchant in recirculating PTFE or PFA immersion baths. The film stack normally comprises 500–1,200 nm of PECVD SiO₂ over 0.8–1.5 µm Al–0.5Cu or Al–1Si metallization with an optional Ti/TiN anti-reflective coating. A representative process set point for 6:1 volume ratio buffered oxide etch is 23 ± 1 °C with 80–120 nm/min thermal oxide removal. Under these conditions, aluminum thickness loss measured by four-point probe remains below 2 nm after 30 min continuous immersion. Selectivity is maintained by buffering ratio, surfactant package, and low trace-metal burden; electronic/EL-grade material filtered at point of use through 0.05 µm PTFE cartridges typically adds fewer than 50 particles/mL at ≥0.2 µm. Etch bath age is a primary production variable. In 8–12 h recirculating bath operation, evaporation of ammonium fluoride increases free fluoride activity, causing silicon dioxide etch rate to rise by 10–20% while aluminum attack accelerates if pH is not corrected. Daily replenishment with electronic-grade NH₄F and HF solutions, verified by ion chromatography, holds pH drift below 0.2 pH units. A strict overetch cap of 20% of the nominal oxide thickness prevents bond pad pits from undercutting the passivation lip. Post-etch cleaning requires overflow rinsing in ultrapure water with resistivity ≥18 MΩ·cm at 25 °C followed by isopropanol vapor drying to prevent water marks on exposed aluminum. Compliance with SEMI C27 is the minimum bulk acceptance specification; incoming lots are further screened by ICP-MS for Fe, Ni, Cr, Cu, Zn, and Na below 10 ppb, because copper contamination above 5 ppb is associated with galvanic pitting at the Al–Cu interface.

What Controls Yield During Sacrificial Oxide Release With Exposed Aluminum in MEMS?

Sacrificial oxide release in MEMS often leaves aluminum bond pads, Al–Si anchors, or CMOS-compatible interconnect exposed to the wet etchant for extended periods. The process is not a short pad-open immersion but a bulk sacrificial etch lasting 10–60 min. The selectivity requirement therefore shifts from 50:1 to above 200:1 in critical structures. For a 1.0–1.5 µm TEOS or LPCVD sacrificial silicon oxide layer, thermal oxide etch rate of 60–90 nm/min at 25 °C can be used, but the exact rate is confirmed by spectroscopic ellipsometry on monitor wafers before production lots. Aluminum film thickness is monitored using sheet resistance with a four-point probe per the production control plan, and a conservative criterion is less than 5 nm equivalent thickness loss for the full release window. In surface micromachining, the weak point is not chemical attack alone but mechanical collapse due to rinse stiction after release. Therefore the etchant formula and rinse sequence are evaluated together: a low-particulate electronic/EL-grade formulation with a non-ionic surfactant reduces surface tension at the rinse transition, but surface tension is still larger than the critical adhesion force of cantilevers below 1 µm gap. For such geometries, the wet release is followed by deionized water dilution, isopropanol displacement, and carbon dioxide supercritical drying. Production-scale observations show that bath contamination from the sacrificial material itself—phosphosilicate glass, for example—raises the aluminum etch rate when the bath is not refreshed after each lot. In a 50-wafer batch, phosphorous accumulation above 50 mg/L in the bath can destabilize the aluminum passivation film. Therefore the etch bath is sampled by ion chromatography after every third batch and replaced when phosphate concentration exceeds 30 mg/L. Filter compatibility is limited to PFA, PTFE, and fluoropolymer wetted surfaces; stainless steel components are excluded because fluoride stress corrosion cracking can release metal ions. The process uses an overflow immersion bath with a recirculation rate of 30–40 L/min to maintain a uniform diffusion boundary layer over 150 mm or 200 mm wafers. Published data for the exact selectivity limit on sub-micrometer gap structures is limited, so lot-specific release tests are mandatory.

Where a-Si TFT backplanes use AlNd/Mo source-drain fan-out lines, the PECVD SiO₂ passivation contact hole is opened with the same high-selectivity chemistry. The target layer is usually 200–400 nm of silicon dioxide deposited at 250–300 °C; the underlying metallization may be a three-layer AlNd/Mo/Ti stack. In display fabrication, the etch tool is often a fully automatic cassette-to-cassette wet station with a heated bath set at 35 ± 1 °C to increase throughput. The higher temperature narrows the selectivity window. A formulation that gives 140–180 nm/min oxide etch at 35 °C may consume more than 10 nm of AlNd per 10-minute contact if the pH is not tightly held. Therefore the pH controller and NH₄F replenishment system are interlocked with the batch scheduler to dose only within a specified temperature band. Underetch below 10% leaves residual silicon dioxide that blocks the subsequent molybdenum plug or ITO contact interface, producing open-circuit defects; overetch above 40% creates an unsupported passivation lip and can expose the aluminum-rich edge of the data line to electrolytic corrosion during subsequent wet cleaning. Electrical test data from display fabs associate excessive aluminum loss with higher contact resistance at AlNd/Mo interfaces because aluminum-neodymium has a higher bulk resistivity than the underlying Mo barrier and lateral thinning reduces the effective contact cross-section. Incoming etchant lots for this segment are controlled for chloride and sulfate below 100 ppb because these anions promote aluminum pitting after drying. Point-of-use filtration at 0.1 µm and high-resolution particle counters are standard on display wet stations.

When Wafer-Level Packaging Opens Dielectric Over Al Pads Before UBM Deposition

In redistributed chip-scale packaging and fan-out wafer-level packaging, the first wet step after incoming wafer inspection is usually opening the polyimide or PECVD SiO₂ passivation over aluminum bond pads before electroless or electroplated under-bump metallization. The selective silicon dioxide/aluminum etchant is selected because the Al pad must remain smooth and free of crystalline residues; any fluoride residue or aluminum pitting degrades the subsequent zincation or sputtered Ti/Cu seed adhesion. In this segment, the exposed pad is not a plain Al pad but may be Al–0.5Cu with a thin TiN top layer. The TiN layer is removed by a separate plasma or peroxide-based etch, leaving the aluminum pad underneath protected by the high-selectivity formulation. Process windows are strongly influenced by pad size and pitch. For 70–100 µm round pads on a 150–200 µm pitch, the oxide film is 0.8–1.2 µm and the etch time is 7–11 min at 23 °C. The selectivity to aluminum is measured on production witness wafers with 1 µm Al film and no TiN; acceptable material loss is below 1 nm for the entire etch time. Higher losses create pad roughness above 3 nm RMS, which can be observed by atomic force microscopy under ISO 25178-2 areal roughness protocols. That roughness changes the nucleation density of electroless nickel and produces non-uniform bump height. Because the subsequent UBM seed layer is sputtered, a pad surface with fluoride residues causes adhesion failure at tape test. The post-etch rinse sequence therefore includes a 10-minute overflow rinse with megasonic energy below 80 W to avoid pad damage. The bath is equipped with a platinum or fiber optic level sensor rather than metallic float switch to avoid cation contamination. For analytical verification, ion chromatography of the bath and inductively coupled plasma mass spectrometry of the rinse water are recorded in lot history. The relevant outbound control is typically less than 1 µg/wafer total sodium, potassium, and calcium on the pad surface.

Discrete power MOSFET and IGBT flows require a high-selectivity oxide etch during pre-metal dielectric etch-back to expose aluminum metallization without damaging thick power metal. The dielectric is often borophosphosilicate glass or undoped silicate glass 0.5–1.5 µm thick, deposited over a 3–6 µm AlSiCu power metallization. The general etch rate is reduced by controlling bath temperature at 21–23 °C to avoid excessive attack at grain boundaries. The aluminum films used in power devices have larger grain size and higher copper content than logic CMOS, so aluminum grain boundary corrosivity is closely monitored by scanning electron microscopy after etch. Production controls include an overetch factor not exceeding 15% because of thick dielectric steps at the edge of power metal. A key incompatibility is the use of this fluoride-based etchant with exposed titanium nitride or titanium tungsten barrier layers in the same tank; those films are rapidly attacked and can shift the bath chemistry, so a short pre-clean step is kept separate. The electronic/EL grade is specified with less than 10 ppb of transition metals, but additional in-line DI water rinse quality and nitrogen blow-off are required to prevent corrosion at aluminum bond pad edges. The standard etch tank is an overflow cell with a weir height calibrated for 150 mm or 200 mm wafers and a return line that maintains laminar flow over the wafer surface at a Reynolds number of approximately 8,000. Batch records from production lines show that selectivity loss occurs when dissolved silicon from the dielectric reaches 1,500–2,000 mg/L in the bath; at this point the aluminum surface begins to roughen even if the pH remains within specification. Bath replacement based on dissolved silicon concentration is therefore more reliable than time-in-tank for extended power device lots.

Aluminum Surface Compatibility in Silicon Dioxide Removal for Thin-Film Hybrid Circuits

Thin-film hybrid circuit fabrication on 99.6% alumina or borosilicate glass substrates requires opening SiO₂ passivation over aluminum conductor traces before wire bonding or solder attach. The aluminum layer is typically evaporated or sputtered 2–5 µm thick, with larger grains and higher room-temperature native oxide than semiconductor pad metallization. The high-selectivity electronic/EL-grade etchant is used at ambient temperature to remove a 0.3–0.8 µm low-temperature SiO₂ passivation layer without roughening the aluminum bond pads. In these non-wafer formats, the substrate is processed in a flat carrier, and the etch bath is usually a rectangular PFA tank with nitrogen agitation at 2–5 L/min. Etch rate is lower than in semiconductor baths because the low-temperature oxide is more porous; process engineers establish rate on product-specific witness substrates rather than using thermal oxide calibration. Aluminum film loss is checked by stylus profilometry across masked steps, and the acceptance limit is typically 10 nm for a 20-minute contact window. A significant limitation in this segment is the use of solder or gold wire bonding after etch; any residual fluoride at the aluminum surface reduces ultrasonic wire bond pull strength. The post-etch rinse therefore uses two-stage cascading DI water overflow followed by 70–80 °C nitrogen blow-off. Production records show that dropping the final rinse resistivity below 10 MΩ·cm increases wire bond failures at pull test under MIL-STD-883 method 2011.7. The etchant in this application is controlled for sulfate and phosphate contamination below 200 ppb because these anions can remain as hygroscopic salts and accelerate open-circuit failure in hermetic packages.