On 300 mm logic production lines, the post-dummy-gate removal planarization of HfO₂/TiN work-function stacks is performed with a potassium-free ceria-based slurry conditioned to pH 4.2–4.8 and a point-of-use dilution of 1:1 to 2:1 with ultrapure water. The formulation addition ratio brings the as-dispensed solids content of 1.8–3.6 wt% to 0.6–1.8 wt% after dilution, while 0.15–0.45 wt% H₂O₂ is injected downstream of the flow controller to passivate the TiN surface. Compliance for this segment is anchored to SEMI F57-0301 for polymer wetted surfaces in slurry distribution, ISO 22412:2017 for particle size distribution by dynamic light scattering, and ISO 14644-1:2015 Class 5 for point-of-use dispensing modules; the slurry is filtered through a 0.5 µm point-of-use filter and maintained at 21–24 °C to keep D50 below 140 nm during recirculation. The as-received slurry viscosity is 1.1–1.8 mPa·s at 25 °C and 100 s⁻¹; after 1:1 dilution, viscosity falls to 0.8–1.1 mPa·s, which reduces spray-bar pressure drop by 15–20% at 200 mL/min. Downstream processing runs on 5-zone airbag-head rotary CMP tools with platen speed 80–110 rpm, head speed 75–95 rpm, downforce 1.5–3.0 psi, backside pressure 0.5–1.2 psi, and slurry flow 150–250 mL/min. The pad stack is a polyurethane IC pad with Shore D hardness 52–58, sub-pad 0.8–1.2 mm closed-cell foam, and in situ diamond conditioning at 0.4–0.8 mm/h cut rate. Endpoint is triggered by motor current and optical reflectance, with a target HfO₂ removal rate of 900–1500 Å/min and TiN removal rate of 350–600 Å/min at 2.0 psi, yielding within-wafer non-uniformity below 5% 1σ and defect density below 15 counts/wafer at 0.12 µm threshold. The slurry is not compatible with amine-based pH adjusters because rapid HfO₂ surface charge reversal causes micro-scratch formation; potassium hydroxide is excluded because residual K⁺ degrades channel mobility. Terminal products are FinFET and gate-all-around logic wafers at 7 nm and smaller design rules, where the remaining HfO₂ gate dielectric thickness is 2.0–3.5 nm and post-CMP oxide loss is held below 30 Å.

At Which Point Does Ceria Loading Suppress TiN Galvanic Corrosion in DRAM MIM Stacks?

In 1x/1y/1z DRAM MIM capacitor flows using ZrO₂/Al₂O₃/ZrO₂ laminates, ceria loading after point-of-use dilution becomes the controlling variable for TiN top electrode corrosion. The formulation addition ratio is set at 1:2 slurry to ultrapure water, giving a working solids loading of 0.8–1.2 wt% ceria; when post-dilution ceria exceeds 1.2 wt%, galvanic attack on the TiN electrode increases surface roughness from 0.25 nm to 0.6 nm Ra, correlating with a drop in capacitor leakage uniformity. To suppress this, 0.05–0.10 wt% 1,2,4-triazole is added at point-of-use, and pH is maintained at 4.5–5.5 with potassium-free acetic acid, never with KOH. Compliance is governed by SEMI F63-0705 for UPW total organic carbon and dissolved oxygen control, SEMI F57-0301 for slurry contact materials, and ISO 22412:2017 for particle size distribution; metrology for metal contamination uses ICP-MS with upper limits of <1 ppb for Cu, <1 ppb for Fe, and <5 ppb for total organic carbon in the dispensed slurry. Zeta potential at pH 4.5–5.5 is held between −25 mV and −40 mV for ceria, which prevents particle agglomeration during recirculation. Planarization is run on an orbital CMP platform with platen speed 60–90 rpm, head speed 55–85 rpm, downforce 1.2–2.5 psi, and slurry flow 120–200 mL/min; the pad is a soft polyurethane with Shore D hardness 45–50 and compressibility 8–12%. Endpoint on the Al₂O₃ stop layer is detected by motor current change, with over-polish limited to 5–10 s to avoid capacitor dielectric thinning. Post-CMP cleaning uses megasonic UPW at 25–40 kHz and 100–200 W input power, followed by dilute NH₄OH scrubber chemistry to remove ceria residue. At slurry temperature above 28 °C, ceria suspension flocculates and D50 shifts from 120 nm to 180 nm, so heat exchangers must hold 21–24 °C. Terminal products are DRAM wafers with MIM capacitor cell capacitance 20–30 fF/cell and equivalent oxide thickness 0.55–0.75 nm at 1x nm design rules.

3D NAND Charge Trap Blocking Dielectric Planarization Window

After conformal deposition of Al₂O₃/HfO₂ blocking oxide over tiered channel-hole structures in 3D NAND, the top-surface topography is subjected to a low-shear ceria touch polish before tungsten word-line fill. The formulation addition ratio is 1:3 slurry to ultrapure water, producing a working solids loading of 0.2–0.8 wt% and pH 3.8–4.4; this oxidizer-free formulation is intentionally free of KOH and sodium salts because aluminum corrosion in alkaline media exceeds 5 Å/min at pH above 8.0. Compliance scope includes SEMI S2-0716 for interlocked slurry distribution equipment, ISO 14644-1:2015 Class 5 for cleanroom equipment, and SEMI F57-0301 for wetted materials; point-of-use filtration at 0.2 µm removes agglomerates larger than 200 nm from the low-solids stream. Downstream processing uses a 300 mm CMP bridge tool with platen speed 50–80 rpm, head speed 45–70 rpm, downforce 0.8–2.0 psi, and slurry flow 100–150 mL/min; pad selection is a closed-cell polyurethane with Shore D hardness 45–55 and surface roughness 2–5 µm Ra after diamond conditioning at 0.3–0.6 mm/h. The endpoint algorithm relies on motor current plus eddy-current fringe-field shift because optical reflectance has limited contrast on transparent Al₂O₃ films. Target step-height reduction is 20–40 Å on the blocking oxide, with dielectric loss below 10–15 Å per polish cycle. An operational boundary occurs at post-polish buff temperature above 26 °C, where the pad surface glazing reduces removal rate by 12–18%; therefore platen cooling is set to 18–22 °C. Terminal products are 64- to 128-layer 3D NAND wafers with charge trap flash memory cells in which the blocking oxide thickness is 4–6 nm and post-CMP surface roughness is held below 0.5 nm Ra to reduce electron leakage.

Ferroelectric Hf_0.5Zr_0.5O₂ layers in FeFET and FeRAM integration require a planarization step after top electrode deposition, but published CMP data for this specific configuration is limited. The formulation addition ratio therefore follows conservative low-solids conditions: 1:2 slurry to ultrapure water dilution, working solids 0.2–0.5 wt% ceria, pH 4.0–6.0, and no alkaline oxidizer because the orthorhombic phase responsible for ferroelectric polarization is degraded by high pH and high shear. Compliance for pilot and pre-production lines is typically aligned to SEMI F57-0301 for slurry contact materials and ISO 14644-1:2015 Class 5 for point-of-use cabinets; equipment safety is assessed under SEMI S2-0716. Polishing is run on 4-zone head tools with platen speed 40–70 rpm, head speed 35–60 rpm, downforce 0.5–1.5 psi, and slurry flow 80–120 mL/min; pad hardness is Shore D 40–48 to minimize mechanical damage to the ferroelectric layer. Endpoint is based on time-domain motor current because the film stack is transparent; over-polish is limited to 10 s. Post-CMP annealing at 400–600 °C in N₂ is required to restore saturated polarization, and published data for exact removal-rate windows in this specific configuration is limited. The trustworthiness boundary is defined by the absence of a consensus industry specification for ferroelectric phase retention after CMP; process qualification therefore relies on test-site electrical data rather than a fixed global standard. Terminal products are embedded nonvolatile FeFET memory cells and FeRAM capacitors with polarization values of 10–20 µC/cm² after wake-up cycling.

When AlGaN Surface Roughening Limits Downforce in GaN MIS-HEMT Gate Dielectric Polishing

In GaN-on-SiC MIS-HEMT fabrication, planarization of ALD-deposited Al₂O₃/HfO₂ gate dielectric stacks must avoid increasing AlGaN barrier roughness, which depresses two-dimensional electron gas mobility. The formulation addition ratio is 1:2 slurry to ultrapure water, with a working solids loading of 0.4–1.0 wt% ceria and pH 4.0–5.0; ammonia and other amine-based buffers are disqualified because they etch GaN at rates above 10 Å/min at pH above 7.5. Compliance is driven by SEMI S2-0716 for equipment safety and ISO 22412:2017 for particle size verification; particle size D50 is maintained below 130 nm and large particle counts at 0.5 µm threshold are kept below 20 counts/mL. Downstream processing occurs on a 150/200 mm CMP tool with platen speed 60–80 rpm, head speed 50–70 rpm, downforce constrained to 1.0–2.0 psi, and slurry flow 80–150 mL/min; a soft polyurethane pad with Shore D hardness 42–50 is conditioned at 0.3–0.5 mm/h. If backside pressure exceeds 0.8 psi, edge chipping on SiC substrates increases; therefore the tool recipe limits backside pressure to 0.3–0.8 psi. Post-CMP anneal at 350–450 °C in forming gas consisting of N₂/H₂ is required to recover interface state density, and surface roughness after polishing is verified by atomic force microscopy to stay below 0.5 nm Ra. Terminal products are AlGaN/GaN HEMT power amplifiers and MMICs for 5G and satellite communications, with gate leakage current density below 1×10⁻⁶ A/cm² at 3 V.

Silicon Wafer Reclaim Buffing After High-K Film Stripping

Reclaimed 300 mm wafers carrying residual HfO₂, ZrO₂, Al₂O₃, and TiN following dry strip and wet etch require a final buffing step to remove sub-surface metal contamination and restore prime-grade surface roughness. The formulation addition ratio is 1:5 slurry to ultrapure water, with working solids 0.1–0.3 wt% silica in a pH 9.5–10.5 potassium-free ammonia/ammonium carbonate buffer; the dilution is prepared in a UPW loop meeting SEMI F63-0705 limits for total organic carbon <5 ppb, dissolved oxygen <10 ppb, and lithium/boron/sodium <1 ppb. Compliance for reclaimed wafer processing is governed by SEMI F57-0301 for wetted components and ISO 14644-1:2015 Class 5 for final cleaning modules; the slurry is filtered to 0.5 µm and recirculated with heat exchangers maintaining 21–23 °C. Downstream processing is carried out on double-side polishing tools with 4-zone platens at speed 30–60 rpm, downforce 0.2–0.5 psi, flow 200–300 mL/min per side, and pad hardness Shore D 55–65; because double-side polish can introduce edge roll-off, the recipe holds center-to-edge removal variation below 5%. Terminal products are reclaimed 300 mm prime-grade test/monitor wafers with global flatness GBIR ≤3 µm, local site flatness SFQR ≤0.13 µm at 26 mm × 8 mm site size, and surface roughness below 0.2 nm Ra; these wafers are not returned to front-end device flows but are used for tool qualification, CMP pad break-in, and particle monitoring.