Wafer-level packaging lines processing 300 mm silicon and fan-out panel substrates consume the largest share of electronic-grade gold plating salt in bump metallization. In these lines, a sputtered TiW/Au seed layer or an electroplated Cu/Ni under-bump metallization stack is patterned with thick photoresist, and gold is electrodeposited through the resist openings in a cup-type fountain plater equipped with platinized titanium anodes and paddle agitation. The high-purity gold sulfite or cyanide citrate electrolyte is maintained at pH 4.2–4.8 and 55–65 °C, with a current density of 2.0–6.0 A/dm². The deposit thickness for subsequent wire bonding or thermosonic flip-chip connection is typically 15–25 µm, with a Knoop hardness of 60–90 HK25 under ASTM B488 Type III purity of 99.9%. Metal impurities above 5 mg/kg for Fe, Ni, Co, Cu, and Pb in the salt produce nodular growth and increase surface roughness because the impurities adsorb preferentially on high-current-density sites. Organic degradation products from photoresist leaching accumulate in the bath and reduce current efficiency at the edge of the wafer; batch-life termination is therefore governed by total organic carbon rather than gold depletion in most production lines. Adhesion failures after wire pull testing are commonly traced to bath contamination by iron from stainless steel transfer piping when anolyte and catholyte compartments are not separated. Salt containers opened in cleanrooms above 60% relative humidity require pre-drying at 80 °C for 24 h before gravimetric bath make-up to prevent weighing drift from absorbed moisture.

Edge Connector Hard Gold Deposits Rely on Cyanide Electrolytes with Cobalt or Nickel Codeposition

Gold fingers on printed circuit boards for PCIe, DDR, and backplane applications are plated in vertical in-line or reel-to-reel cells in which the board edge is immersed in a hard gold bath. The electronic-grade gold salt is blended with proprietary cobalt or nickel salts to produce codeposits containing 0.1–0.3 wt% Co or Ni, raising hardness from 60–90 HK25 to 130–190 HK25. The electrolyte is maintained at 40–60 °C and pH 3.8–4.5, with current densities of 1.0–4.0 A/dm². Nickel chloride or nickel sulfamate is applied as an underplate at 2.5–5.0 µm, while hard gold thickness is held at 0.75–1.25 µm. Porosity at this thickness is a direct function of organic brightener concentration; excess brightener increases ductility but creates microscopic voids revealed by ASTM B735 nitric acid vapor tests. Contact resistance after 500 mating cycles is required to remain below 10 mΩ according to IEC 60512-2-1, and surface wear resistance is typically evaluated by reciprocating wear with a 100 g load over 10,000 cycles. Bath contamination by tin or lead above 10 mg/kg causes dull deposits and reduces solder wetting after press-fit assembly, so EL-grade salt with single-metal impurities below 5 mg/kg is specified. Rack plating lines running at the lower current density bound produce a finer grain size but reduce throughput; production facilities therefore operate near 3.5 A/dm² only when anode-to-cathode spacing is maintained within ±5 mm to avoid edge burn on panel borders.

Skin depth constraints in millimeter-wave interconnects, specifically in 28 GHz and 77 GHz automotive radar phased-array transceivers, control the minimum gold thickness on inner conductors and connector bodies. At 28 GHz the skin depth in gold is approximately 0.45 µm, and at 77 GHz it falls to about 0.27 µm; manufacturers therefore specify gold thickness of 0.8–1.5 µm to ensure that more than three skin depths carry current and that insertion loss remains stable after thermal cycling. Cyanide-free gold sulfite baths are preferred for these parts because cyanate decomposition products can co-deposit as organic inclusions that raise surface roughness from Rz 0.2–0.4 µm to above Rz 0.8 µm. The bath is operated at 45–60 °C and pH 8.5–9.5 with a current density of 0.5–2.0 A/dm² to maximize throwing power into 0.3 mm inner bore diameters. Ferromagnetic impurities in the gold salt are critical for passive intermodulation performance in base station connector arrays; Fe, Ni, and Co are each limited to 5 mg/kg, and nonvolatile residue after calcination is specified below 10 mg/kg. Thickness distribution across a 12-port connector body is measured by X-ray fluorescence on 32 points, and the coefficient of variation must be below 8% to avoid impedance mismatch at 77 GHz. Bath aging under high air agitation accelerates sulfite oxidation to sulfate; sulfate concentration above 40 g/L causes deposit dulling and is controlled by batch sulfite replenishment rather than continuous feed.

When MEMS Microswitches Demand Zero Trace Organic Brightener Carryover

RF MEMS ohmic switches and cantilever beam relays represent a process conflict between throughput and deposit cleanliness. The gold salt must produce a deposit soft enough to maximize contact area under a 20–80 µN actuation force, but the bath must remain free of organic brighteners that raise stiction and increase adhesion work after release. Gold sulfite electrolytes are operated at pH 8.0–9.5 and 45–55 °C with current density limited to 0.5–1.5 A/dm² because above 2.0 A/dm² the deposition becomes mass-transport-limited and produces nodular growth on beam edges. The plated gold thickness on RF MEMS contacts is 2.0–5.0 µm, with hardness between 40 and 70 HK25, which is lower than hard gold used on connectors and incompatible with sliding wear but necessary for low contact resistance below 2 mΩ at 1 V and 1 mA. The salt lot used for MEMS plating is filtered through 0.05 µm membranes and sampled for total organic carbon; lots exceeding 200 mg/L of TOC in the prepared bath are rejected because organic carbon reduces the gold grain size and increases the average roughness from 1.5 nm to over 5 nm. Adhesion to the silicon nitride or silicon oxide release layer is tested by tape pull after a 300 °C vacuum bake; failures at the gold-to-seed interface are frequently caused by trace sulfate carryover rather than mechanical stress in the cantilever. Published data for organic brightener thresholds below 0.1 vol% in sulfite gold baths for MEMS is limited; process qualification therefore must rely on wafer-level contact resistance mapping rather than bulk bath analytics alone. The same bath cannot be shared with edge connector hard gold electrolytes because cobalt or nickel contamination above 2 mg/kg changes the MEMS contact surface energy and increases stiction after the first actuation cycle.

High-Temperature Die Attach Gold Plating for GaN and SiC Device Metallization

Wide-bandgap power devices for 650 V and 1200 V modules require gold surfaces on die backside metallization for Au80Sn20 eutectic die attach. The gold layer is deposited over electroless nickel or sputtered Ti/Ni adhesion layers at 1.5–3.0 µm, and it must remain oxide-free through storage periods of up to 12 months before soldering. The gold salt used in this process is a cyanide citrate type maintained at 60–70 °C and pH 4.2–4.8, with current density of 1.0–4.0 A/dm² and gentle cathode rod agitation. The resulting soft gold has a hardness of 60–90 HK25 and a purity of 99.9% or greater, but the limiting impurity is not base metals; thallium at concentrations above 2 mg/kg in the salt changes grain structure and accelerates gold dissolution into molten Au80Sn20, shifting the reflow profile by 5–8 °C. Solder wetting is evaluated by the spread ratio of a 3.0 mm diameter Au80Sn20 preform at 305 °C under forming gas, with a required wetting area above 90%. Module manufacturers specify gold thickness uniformity of ±0.25 µm across a 200 mm wafer; this is achieved by shielded anode configurations rather than by increasing current density, because higher current density roughens the deposit and creates void lines at the die edge after reflow. A documented incompatibility exists with photoresist strippers containing N-methylpyrrolidone, which leave residues that inhibit gold nucleation on the sputtered seed layer; oxygen plasma descum is required before plating.

Implantable pulse generator assembly lines that electroplate titanium alloy feedthroughs and Pt-Ir electrode contacts use salt lots certified against ISO 10993-5 for cytotoxicity and ISO 10993-12 for extractable heavy metals. Gold sulfite rather than cyanide formulations is specified because the absence of free cyanide simplifies cleaning validation and reduces the risk of cyanide residue on alumina ceramic surfaces. The bath is maintained at pH 7.0–9.0 and 45–55 °C with a current density of 0.5–1.5 A/dm², and gold thickness is limited to 1.0–2.0 µm on implantable contacts. The EL-grade salt is supplied with certificates of analysis listing Fe, Ni, Co, Cu, Pb, and Cd below 5 mg/kg and endotoxin below 0.25 EU/mL when the prepared electrolyte is filtered through a 0.2 µm capsule filter. Adhesion testing follows ASTM B571 for bent-wire specimens; delamination of more than 5% of the plated area after thermal cycling from 37 °C to 200 °C is cause for rejection. Porosity is tested by gel electrography at 4.5 V in 0.1 M KCl, and a single pore larger than 0.25 mm is not acceptable on a sealed feedthrough surface.

Can High-Speed Gold Plating Baths Maintain Solderability Without Nickel Underplate?

Hybrid microcircuits and ceramic chip carriers sometimes require solderable gold pads on thick-film gold conductors, where a nickel underplate is not always compatible with the conductor composition. The critical boundary condition is not plating speed but the thickness of gold that dissolves into the solder joint. For Sn63/Pb37 and SAC305 alloys, gold concentrations above 2.0–3.0 wt% in the solder fillet form AuSn4 platelets that reduce shear strength by 30–50%; consequently, gold thickness on solderable terminations is held to 0.5–1.0 µm, not the 1.5–3.0 µm used for Au80Sn20 die attach. The gold salt is operated at pH 5.8–6.5 and 50–60 °C with current density of 0.5–2.0 A/dm² to avoid burning at the edge of screen-printed gold conductors. A neutral citrate or sulfite formulation avoids attack of the underlying silver-palladium or gold paste. MIL-STD-883 method 2003 is used to assess solderability after 8 h steam aging; wetting must exceed 95% of the pad area. Process control records for this application track gold thickness by X-ray fluorescence every 15 min, because a drift of 0.3 µm changes the gold-to-tin ratio from 1.0 wt% to 2.5 wt% on a 100 µm solder bump. Printed wiring assemblers occasionally request thicker gold for corrosion resistance; that request is incompatible with soldering without complete gold removal by a solder dip before joint formation.