| HS Code | 159836 |
| Product Level | EL Grade (Electronic Grade) |
| Pad Style | Flat |
| Groove Type | Non-grooved |
| Base Material | Polyurethane |
| Hardness | Shore D 58 |
| Density | 0.78 g/cm3 |
| Thickness | 1.27 mm |
| Surface Roughness | Ra 0.3 μm |
| Flatness | ±5 μm |
| Porosity | Microporous closed-cell foam |
| Chemical Resistance | Excellent resistance to acids, alkalis, and common slurry chemicals |
| Surface Condition | Unfilled, non-patterned polishing surface |
| Application | Semiconductor wafer CMP planarization |
As an accredited Flat Non-Grooved CMP Polishing Pad Electronic/EL Grade factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.
| Packing | Each pad is individually sealed in cleanroom packaging to prevent contamination, with 20 pads per case. |
| Container Loading (20′ FCL) | 20′ FCL: Flat non-grooved CMP pads, EL grade, securely packed in export cartons, loaded in standard 20-foot container. |
| Shipping | These electronic/EL-grade flat, non-grooved CMP pads ship in cleanroom-sealed, moisture-barrier packaging within rigid cartons to prevent contamination and deformation. Pallets are stretch-wrapped and climate-controlled where required. Standard ground freight applies; no hazardous materials declaration needed. Handle carefully, store flat, and avoid extreme temperatures during transit. |
| Storage | Store in a clean, dry, climate-controlled area away from direct sunlight, dust, and chemical vapors. Maintain ambient temperature between 15–30°C and moderate humidity, keeping the original sealed packaging intact until use. Handle with clean gloves to prevent contamination. Avoid folding, compressing, or exposing the pad to moisture. Use within manufacturer-recommended shelf life for optimal performance. |
| Shelf Life | Shelf life typically 12 months from manufacture when stored sealed in original packaging, away from moisture and contaminants. |
In high-volume 300 mm front-end logic wafer planarization, the flat non-grooved CMP polishing pad is inserted at the oxide interlayer dielectric buff step where the uninterrupted polymer surface shifts slurry residence time and wafer-scale contact uniformity relative to grooved pads. The cast polyurethane matrix is manufactured with an isocyanate-to-polyol ratio of 0.98–1.03, yielding a Shore D hardness of 58–65 when tested in accordance with ASTM D2240-15; tensile elongation at break is controlled to 180–250% under ASTM D412-16 to limit pad-debris generation during break-in. All pad contact materials are screened against REACH EC 1907/2006 candidate-list substances and RoHS Directive 2011/65/EU Annex II restricted substances, and the pad is qualified for ISO 14644-1:2015 Class 3 cleanroom transfer without surface-shedding above 0.1% by mass. The paired fumed silica slurry is formulated at 1.0–2.5 wt% SiO₂ solids, adjusted to pH 10.8–11.0 with dilute KOH, and delivered at 120–160 mL/min per 300 mm wafer; this solids-addition ratio maintains a controlled coefficient of friction on a non-grooved pad while avoiding pad-glaze accumulation. On a four-head rotary CMP platform with a 300 mm wafer carrier, the process window uses platen speed of 60–90 rpm, carrier speed of 50–65 rpm, and downforce of 2.5–4.0 psi; ex-situ conditioning is performed with a 100-grit diamond disk at 35–40 N downforce for 10–15 seconds per wafer. Terminal products include 28 nm-node and below logic system-on-chip devices, graphics processors, and application-specific integrated circuits for data-center and mobile platforms.
The STI step consumes the flat pad where high-topography oxide overburden must be removed without breaking through nitride masks. The process recipe uses a ceria-based slurry with a CeO₂ solids addition ratio of 0.5–1.5 wt% and a polyacrylic acid dispersant at 0.05–0.10 wt% of slurry mass; slurry pH is held at 4.0–5.0 to maintain electrostatic selectivity between SiO₂ and Si₃N₄ surfaces. Pad hardness is qualified at Shore D 60–70 per ASTM D2240-15, and compression set is monitored below 12% after 22 h at 70°C per ASTM D395-18 to prevent hysteresis that would alter low-pressure contact. Equipment integration follows SEMI S2 for safety and environmental compatibility, while pad packaging and transport comply with ISO 14644-1:2015 Class 5 to control contamination at the wafer edge. On 200 mm and 300 mm rotary CMP tools, the pad is run at platen speed 50–70 rpm, carrier speed 40–60 rpm, and downforce 3.0–4.5 psi; optical endpoint detection triggers within 10–15 seconds after nitride exposure, after which a deionized-water rinse step removes residual ceria. Production-line failure modes include pad glazing when ex-situ conditioning with a 90-grit diamond disk is deferred beyond 6–8 wafers, causing a drop in oxide removal rate and a rise in nitride loss. Terminal device types include embedded microcontrollers, DRAM, NAND flash memory, and analog mixed-signal integrated circuits fabricated in planar bulk CMOS flows.
After bulk copper overburden has been cleared on a grooved pad, the remaining Ta/TaN barrier film and ultralow-k dielectric demand a flat non-grooved pad contact that lowers scratch density but reduces slurry-transport capacity, so the barrier step is operated with a highly dilute slurry and higher flow rate. The barrier slurry is prepared with a colloidal silica solids addition ratio of 0.1–0.3 wt%, hydrogen peroxide at 0.8–1.2 wt%, benzotriazole corrosion inhibitor at 0.1–0.2 wt%, and pH adjusted to 9.5–10.5 with dilute ammonium hydroxide; the low abrasive load prevents accumulation of silica agglomerates on the pad surface and maintains defect density below wafer qualification thresholds. Cleanroom handling follows ISO 14644-1:2015 Class 4, and the pad is qualified by 24 h immersion in pH 9.5–10.5 slurry to ensure hardness drift does not exceed 2 Shore D units under ASTM D2240-15; materials comply with RoHS Directive 2011/65/EU Annex II and REACH EC 1907/2006 SVHC screening. In a two-platen or three-platen 300 mm CMP sequence, the barrier step operates at platen speed 80–100 rpm, carrier speed 60–75 rpm, downforce 1.5–2.5 psi, and slurry flow 150–200 mL/min; in-situ pad conditioning with a 100-grit diamond disk at 25–30 N is run every 3–5 wafers to manage glaze and retained slurry solids. Terminal products are sub-10 nm logic application processors, artificial-intelligence accelerators, high-speed networking ASICs, and other devices where copper interconnect defectivity directly affects yield.
Edge flatness on silicon carbide substrates degrades when the pad cannot bridge the wafer edge after lapping because SiC is mechanically hard and transmits local pressure non-uniformity into subsurface damage. The final-polish recipe uses a colloidal silica slurry with a solids addition ratio of 1.0–2.0 wt% SiO₂, an oxidizer addition of 0.2–0.5 wt% sodium persulfate relative to slurry mass, and pH maintained at 8.5–9.5; the oxidizer ratio must be controlled within ±0.05 wt% because excessive persulfate increases silica gelation and edge stain. The pad is qualified for Shore D hardness 55–65 under ASTM D2240-15 and for polished monocrystalline silicon wafer flatness compatibility under SEMI M1; post-polish inspection is performed in an ISO 14644-1:2015 Class 4 cleanroom to avoid particle decoration before epitaxial layer growth. On 150 mm and 200 mm single-side CMP equipment, the substrate is processed at platen speed 30–50 rpm, carrier speed 25–35 rpm, downforce 3.0–5.0 psi, and slurry temperature 45–55°C; conditioning is completed every run with a 70-grit diamond disk at 30–40 N to regenerate pad surface roughness. Published removal-rate data for flat non-grooved pads in SiC final polish is limited compared with oxide CMP, so process qualification is typically confirmed by wafer-fab pilot runs rather than vendor-supplied tables. Terminal products include 650 V, 1,200 V, and 1,700 V silicon carbide MOSFETs, Schottky barrier diodes, and power modules for photovoltaic inverters, electric-vehicle traction drives, and industrial motor controls.
A TSV reveal process on 300 mm temporary-bonded silicon interposers uses the flat pad after wafer back-grinding to remove silicon and expose copper-filled through-silicon vias, where local dishing across dense and isolated via arrays must be held to minimal difference. The copper bulk step is formulated with an aluminum oxide abrasive addition ratio of 0.5–1.5 wt%, glycine at 0.3–0.6 wt%, benzotriazole at 0.1–0.2 wt%, and pH 6.5–7.5; the subsequent silicon reveal step uses a silica slurry at 1.0–2.0 wt% solids and pH 8.0–9.0. The pad and sub-pad stack are qualified for tear strength under ASTM D624 and for equipment safety under SEMI S2; temporary-bonded wafer handling is performed in ISO 14644-1:2015 Class 5 to prevent adhesive residue from contaminating the pad surface. On integrated CMP platforms with 300 mm wafer carriers, the reveal sequence uses downforce 1.0–2.0 psi, platen speed 60–80 rpm, and in-situ friction endpoint monitoring; a low downforce limit is maintained because flat non-grooved pads generate higher contact area and can amplify edge pressure variation if over-loaded. Production-scale failure modes include slurry pooling at the wafer center when flow rates fall below 100 mL/min, leading to copper dishing reversal; this is controlled by edge-directed slurry dispense and a 100-grit diamond conditioning cycle every 2–3 wafers. Terminal products are high-bandwidth memory stacks, silicon interposers, and 2.5D/3D advanced packages for data-center processors and AI modules.
Directly after diamond mechanical polishing and surface cleaning, c-plane sapphire substrates enter a flat non-grooved final CMP step to remove subsurface damage and generate the epi-ready surface required for III-nitride deposition. The final-polish slurry is made up at a silica solids addition ratio of 2.0–5.0 wt%, with an organic amine surfactant added at 0.05–0.10 wt% and pH adjusted to 10.5–11.0; the surfactant addition ratio is critical because too little causes pad-wafer stiction and too much leaves carbon residue after cleaning. The pad is qualified for Shore D hardness 50–60 per ASTM D2240-15 and for surface-shedding behavior under ISO 14644-1:2015 Class 3 transfer; all pad materials meet RoHS Directive 2011/65/EU Annex II restrictions. On 2-inch to 6-inch sapphire wafer polishing machines, the process runs at platen speed 20–40 rpm, carrier speed 15–25 rpm, downforce 0.5–1.0 psi, and slurry flow 80–120 mL/min; the low downforce window is required because sapphire’s thermal conductivity and hardness concentrate heat at contact asperities, and raising downforce above 1.5 psi on a non-grooved pad produces visible micro-scratch and edge pitting. Pad conditioning is performed with a soft brush and deionized water between lots, not aggressive diamond, to preserve the flat surface texture. Terminal products include epi-ready sapphire substrates for GaN-on-sapphire light-emitting diodes, micro-LED arrays, radio-frequency HEMT devices, and surface-acoustic-wave or bulk-acoustic-wave filter wafers; published removal-rate data for this specific non-grooved configuration in sapphire finishing is limited, so substrate manufacturers typically qualify pad lots by atomic-force-microscope roughness below 0.2 nm Ra on test wafers.
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In the electronic-grade planarization sector, the Flat Non-Grooved CMP Polishing Pad Electronic/EL Grade is supplied as configuration FN-CMP-EL-500/2.0, where the suffix designates a 500 mm platen diameter and a 2.0 mm nominal thickness. Alternative platen diameters of 610 mm, 710 mm, and 730 mm are available with thicknesses of 1.27 mm and 2.54 mm. The pad surface is produced without continuous macro-grooves, perforations, or flexure-cut channels; the working face instead presents a continuous polyurethane microporous structure. Electronic/EL grade lot acceptance includes extractable cation analysis by inductively coupled plasma mass spectrometry after 1 h deionized-water extraction at 80 °C, with typical upper limits of 5 ppm total Na, K, Fe, and Cu and 1 ppm Cu per ISO 17294-2:2016. Cleanroom packaging is performed under ISO 14644-1:2015 Class 5 conditions. This configuration is intended for oxide, nitride, and barrier-layer chemical mechanical polishing where low defectivity and high die-level planarity dominate removal-rate throughput.
Removal of macroscopic grooves eliminates the primary lateral distribution channels that in grooved pads produce a stable slurry film at platen speeds of 30–80 rpm. In a flat non-grooved architecture, slurry transport becomes dependent on pad microtexture, wafer-to-pad relative velocity, and head oscillation. On production polishers with 300 mm wafer platens, the resulting slurry film thickness is frequently 40–70 µm, compared with 100–180 µm for scored pads; this thinner film lowers hydrodynamic lift and increases the proportion of direct wafer–pad contact, which raises local friction and heat generation. Platen temperature spikes above 60 °C are therefore possible during high-pressure copper clearing if slurry flow rate drops below 150 mL/min. Conditioning must be adjusted accordingly: a diamond disk with 100–200 µm grit and a downforce of 5–9 N/cm is typically required before every lot and for 30–60 s in situ intervals to regenerate microtexture. In production environments, failure to maintain conditioning regularity produces pad glazing, an increase in coefficient of friction from 0.3–0.5 to above 0.8, and rising scratch defects.
Because slurry particles are not captured and retained in grooves, residence time on the pad surface decreases. For fumed silica slurries with mean particle size 20–50 nm, this can reduce chemical reaction time and lower blanket removal rates by 10–20% relative to grooved pads under identical downforce and platen speed. The loss in bulk rate is offset by improvement in planarization efficiency at features with 0.18–0.35 µm pitch and by reduced slurry recirculation that carries agglomerates. The flat pad also shows lower sensitivity to groove-induced slurry film variation across the wafer edge, but this benefit is process-window dependent and is not preserved if pad grooving is replaced by severe subpad stack compression.
Mechanical and chemical release data for the FN-CMP-EL configuration are summarized in Table 1. The values represent typical lot-release ranges, not maximum process capabilities; applications that operate outside these ranges require qualification on a specific polisher platform.
| Property | Test method | Typical value or acceptance |
|---|---|---|
| Hardness, Shore D | ASTM D2240-15(2021) | 52–65 |
| Density | ASTM D792-20 | 0.45–0.75 g/cm³ |
| Mean pore diameter | ISO 15901-1:2016 | 20–45 µm |
| Compressive tangent modulus at 0–50 kPa | ASTM D575-91(2018) | 8–25 MPa |
| Tensile strength | ASTM D412-16 | 10–18 MPa |
| Elongation at break | ASTM D412-16 | 60–120% |
| Surface roughness, Ra | ISO 4287:1997 | 0.2–0.8 µm |
| Total extractable non-volatile residue, 24 h DI water at 60 °C | Gravimetric after ISO 17294-2:2016 filtrate preparation | <0.5 wt% |
| Adhesion, pressure-sensitive backing | ASTM D3330 Method A | ≥12 N/25 mm |
Because the pad is produced from polyurethane, prolonged exposure to organic solvents or slurries with pH outside 2–12 can hydrolyze ester-based segments and shift hardness. Oxidizer chemistries containing hydrogen peroxide up to 10 wt% are generally compatible when slurry temperature remains below 50 °C; above this threshold, swelling of 0.5–1.5% by pad volume has been observed in immersion tests. Pads should be pre-conditioned with a diamond disk before first use and stored at 15–30 °C and 30–60% relative humidity; storage outside these bounds can increase water absorption and alter the tack of the pressure-sensitive adhesive. The electronic/EL grade is not formulated with phthalate plasticizers, and extractable antimony, arsenic, and mercury levels are controlled below 1 ppm for REACH-facing supply chains.
On copper bulk and barrier clearing lines, the flat non-grooved pad is typically assigned to the final platen following a grooved bulk pad. Typical process conditions are downforce 1.5–3.0 psi (10.3–20.7 kPa), platen speed 90–110 rpm, head speed 84–104 rpm, and slurry flow 150–250 mL/min. Under these conditions, the continuous contact area provides lower local pressure variation at the die edge and reduces edge-over-erosion in copper lines with 0.13 µm and 0.09 µm technology nodes. The absence of groove-induced slurry film variation is particularly relevant during barrier tantalum/tantalum nitride clearing, where overpolish windows are typically 10–20% of main polishing time. If the pad is applied too aggressively—downforce above 4.0 psi (27.6 kPa)—the thinner slurry film can produce localized hot spots and chatter marks on brittle low-k dielectrics; published data for this specific configuration at such conditions is limited, and tool-specific DOE is required.
For oxide buffing and shallow-trench isolation polishing, the pad is operated with ceria or fumed silica slurries at pH 9–11. The flat surface reduces microscratch formation during the final 20–60 s overpolish step, but removal rate stability is more sensitive to pad-window conditioning than in grooved alternatives. On rotary polishers with 200 mm and 300 mm wafers, batch-to-batch removal-rate drift remains below 5% when the diamond conditioning disk is replaced before 200 wafer-hours and platen temperature is controlled within ±2 °C of the qualification set point. Use of the pad for tungsten contact planarization is possible but requires higher slurry flow than grooved pads because tungsten slurries with 0.5–1.0 wt% abrasive loadings tend to accumulate near the wafer bevel.
For defect-sensitive automotive and RF devices, the flat non-grooved pad is selected because groove-induced slurry recirculation is eliminated. Macro-grooves on standard pads can entrain agglomerated slurry particles and generate scratch counts of 0.05–0.20 defects/cm² after abrasive break-in; non-grooved pads with closed microtexture are typically qualified when defectivity budgets fall below 0.10 defects/cm² at 0.2 µm detection. Laser scanning wafer inspection using SP2 or equivalent tools is used to verify scratch and particle adders. In wafer-level chip-scale packaging redistribution-layer polishing, the flat pad yields lower erosion over 2/2 µm line/space copper features because the continuous pad plane reduces asperity-driven local polish rate differences. However, the flat architecture is not suitable for all slurry formulations: ceria-based oxide slurries with large particle size distributions may require intermittent ultrasonic pad cleaning to prevent accumulation at the wafer edge, and pads used with high-solids slurries above 1 wt% abrasive loadings require post-polish dechuck inspection for particulate buildup.
A comparative architecture summary is provided in Table 2. The values are representative production-process ranges, not fixed specifications, and should be re-evaluated for each slurry chemistry and polisher platform.
| Parameter | Flat non-grooved electronic/EL pad | Grooved production pad |
|---|---|---|
| Working contact area fraction | 90–100% | 55–75% |
| Slurry film thickness | 40–70 µm | 100–180 µm |
| Slurry residence time | Shorter; dependent on microtexture regeneration | Longer; groove volume retains slurry |
| Blanket silica slurry removal rate | 10–20% lower than grooved pad at equal conditions | Higher bulk rate, lower die-level planarity |
| Defect density after pad break-in | 0.05–0.12 defects/cm² at 0.2 µm | 0.08–0.20 defects/cm² at 0.2 µm |
| Edge planarization efficiency for ≤0.35 µm pitch | Higher | Moderate; edge exclusion often larger |
| Conditioning frequency | Every lot plus 30–60 s in situ intervals | Continuous or every wafer at lower downforce |
| Minimum recommended slurry flow | 150 mL/min for 300 mm platen | 100–150 mL/min typical |
During qualification of the flat non-grooved electronic/EL pad on a 300 mm copper barrier polishing platform, edge exclusion was maintained at 3 mm while post-cleaning particle adders were logged below 25 particles per wafer at 0.2 µm using a defect inspection tool. The pad was conditioned with a 100 grit diamond disk at 6 N/cm downforce and 90 rpm platen speed, and the barrier clearing time remained within 55–70 s for tantalum/tantalum nitride stacks over copper with a 1.5 psi (10.3 kPa) main polishing downforce. The process was sensitive to pad break-in cycles: fresh pads exhibited higher initial friction and required 3–5 dummy wafers before scratch counts fell below the 0.10 defects/cm² threshold.
For front-end shallow-trench isolation polishing, stable removal rates were observed when the pad was paired with ceria slurry at 0.5 wt% solids and pH 10–11, with platen temperature controlled at 40–45 °C. Under these conditions, the flat non-grooved pad produced lower oxide erosion in 0.25 µm pitch shallow-trench isolation features compared with an equivalent grooved pad, but the removal-rate window narrowed by approximately 15% and required tighter slurry flow control at 200–250 mL/min. Published data for this specific configuration on advanced-node gate-last replacement metal gate polishing is limited; process transfer requires wafer-level topography validation by atomic force microscopy or optical profilometry per ISO 25178-2:2021.
