In wafer-level packaging lines producing copper pillar bumps, positive-tone DNQ-novolac resists with film thickness between 40 µm and 120 µm are applied by spin coating, soft-baked, exposed, and then used as plating moulds for electroplated copper pillars of 25–50 µm height. The resist shell after copper plating is chemically cross-linked at its outermost surface by contact with the acidic copper sulphate or copper methanesulfonate bath. Strip is executed in an exhausted automated wet bench fitted with dual-frequency megasonic transducers at 40 kHz and 1.0 MHz; power density is mapped to 0.5–1.5 W/cm² across the wafer carrier. The bath is charged with undiluted EKC-265 because the corrosion inhibitor package is balanced for the supplied solvent-water equilibrium. Site-specific trials have demonstrated that adding more than 5% deionized water to compensate evaporative loss can shift the copper etch rate above the 1 Å/min acceptance limit during a 60-minute exposed-pad exposure. The standard sequence is two immersion stages of 15–25 minutes each at 65–75 °C, with a nitrogen-bubbled overflow rinse vessel between stages to remove dissolved novolac drag-out. Endpoint is confirmed by automated optical microscopy at 200× magnification and, for released lots, scanning electron microscopy on 10 pillars per wafer at 10 kV accelerating voltage. The acceptance criterion is sidewall residue of less than 0.1 µm² per pillar. The cleaned copper pillars then proceed to SnAg cap deposition and reflow; organic residue on the pillar sidewall creates a non-wetting region during solder reflow and appears as a void in CSAM after moulding.

What Limits the Processing Window After SnAg Solder Bump Reflow?

Stripping of 20–60 µm positive resist from wafers that have completed SnAg solder bump reflow is constrained by tin oxide dissolution and the exposure of aluminium I/O pads. The reflow temperature of 240–260 °C partially carbonizes the resist at the bump interface and forms a graphitic shell that resists simple solvent swelling. Immersion in heated EKC-265 at 70–80 °C for 20–30 minutes penetrates the carbonized crust only when megasonic agitation is maintained at 0.8–1.2 W/cm²; without megasonic energy, comparable thickness can require more than 60 minutes. The extended exposure depletes the aluminium pad thickness budget of 0.8–1.2 µm; pad thinning is measured by stylus profilometry after strip and compared with pre-strip baseline. Aluminium corrosion is suppressed by the inhibitor system, but the inhibition margin narrows as dissolved carbon in the bath exceeds 150 g/L. Above this level, qualification lots should include an electrochemical immersion test on 99.5% aluminium foil per ASTM G1-03, with a maximum accepted mass loss of 0.5 mg/cm² over 30 minutes. A further clearance issue occurs when the post-strip rinse is delayed beyond 60 seconds after the wafer cassette exits the hot stripper; evaporative cooling deposits a viscous amine film on the bump surface. The first rinse uses DI water at 50–60 °C and 18 MΩ·cm resistivity, followed by an isopropanol spray at 0.5–1.0 MPa to remove droplets trapped under 40–60 µm tall bumps. Final inspection is performed by dark-field automated optical inspection; the release limit is typically 5 residue-related defects per 300 mm wafer.

RDL Post-Plating Residue Clearance on 300 mm Wafers

Redistribution-layer processing uses thin positive resists of 5–15 µm to define electroplated copper lines of 2–5 µm width and 5–8 µm thickness over polyimide or silicon-oxide passivation. The stripper is applied in a full-wafer cassette bath or in a single-wafer spray chamber; the bath configuration uses a recirculation pump rated at 20–30 L/min and 0.2 µm PTFE filtration to control polymer gel particles. The rate-limiting step is not bulk dissolution but penetration of the stripper into the resist foot between the copper sidewall and the passivation, which is 0.2–0.8 µm wide after seed-layer etch. A two-stage thermal profile is used: the first 5 minutes at 65 °C swells the resist; the following 8–12 minutes at 75 °C dissolves the released fragments. If the second stage exceeds 15 minutes, atomic force microscopy on 10 µm scan windows shows copper line edge roughness above 0.3 µm RMS, because the stripper begins to attack the copper seed-layer interface. Rinse is a three-step sequence of ambient DI water, hot DI water at 55 °C, and nitrogen blow-off at 0.2 MPa. Final rinse water is monitored for pH and total organic carbon; release limits are derived from ASTM D5127-13 water quality guidelines and are typically set at 50 ppb TOC per wafer. The completed RDL wafer is tested by four-point probe; any residue bridging between 5 µm pitch copper lines lowers measured isolation resistance below 1×10⁹ Ω and fails the wafer-level test map.

On fan-out panel lines, dry-film stripping imposes a different boundary-layer profile from round-wafer processing. Dry-film resists of 30–80 µm are laminated on 520 mm × 610 mm reconstituted panels and used as plating masks for copper redistribution conductors. The panel format produces lower fluid velocity at the panel corners; resist removal time on corner dies is 2–3× longer than at the centre. A vertical batch stripper with 40 kHz ultrasonic transducers along both sidewalls is operated at 70–78 °C. The transducer power density is limited to 0.4–0.8 W/cm² because higher levels have caused panel warpage and delamination at the moulding compound edge. EKC-265 is charged at 100% as supplied; evaporated solvent is replenished with fresh solution rather than water to maintain inhibitor concentration. The bath is sampled every 4 hours. Kinematic viscosity measured by ASTM D445-21 is used as a surrogate for dissolved dry-film loading; new-bath values are typically 4–6 mm²/s, and the warning limit is 2× the new-bath value. The transfer from strip bath to rinse tank is completed within 45 seconds to prevent edge residues from drying. The rinse protocol uses two counterflow DI water tanks at 45 °C followed by air-knife blow-off at 0.3 MPa. After drying, the panels move to moulding and ball placement; terminal products include fan-out wafer-level application processors and power-management packages.

Exposed Aluminium Pads Narrow the Strip Window

The exposed aluminium pad on a mixed-metallization bump wafer is the primary compatibility constraint for an alkaline stripper. In the EKC-265 process, aluminium etch rate is a function of bath temperature, water content, dissolved resist concentration, and inhibitor depletion after repeated evaporation cycles. Coupon testing per ASTM G1-03 on 99.5% aluminium is performed at 70 °C and 80 °C for 30 minutes; the pass/fail limit is commonly set at 0.3 mg/cm² per 30 minutes at 70 °C, although the exact acceptance boundary varies by device pad metallization. Published data for the exact EKC-265 aluminium etch rate on mixed-metallization test structures is limited; each line is therefore required to maintain its own coupon baseline before first lot release. Stripping time for 50 µm resist is bounded by incomplete residue clearance at the low end and aluminium pad thinning at the high end. In a 200 mm wafer line with 90-minute bath turnover cycles, the aluminium etch rate can drift from 0.1 µm/hour to above 0.5 µm/hour when the bath is replenished with deionized water rather than formulated solvent. This shift corresponds to a change in the solvent-water azeotrope and depletion of the corrosion inhibitor at the metal surface. Open-circuit potential measurements in a three-electrode cell with a saturated calomel reference electrode monitor inhibitor effectiveness; a shift above +150 mV within 10 minutes indicates the pad has transitioned from passive to active dissolution. Post-strip SEM at 5 kV is used to confirm the absence of pitting. The devices are subsequently wire-bonded; aluminium pad thinning below 0.2 µm is correlated with lower ball shear strength in assembly.

When Pre-Wet Rinsing Is Omitted in Thick Dry Film Removal

When the dry-film resist has been exposed to a CF4-based descum or has been electroplated in a low-pH copper bath, the top 1–3 µm of the film forms a hardened crust with reduced solvent permeability. Direct immersion into hot EKC-265 without a pre-wet step causes the crust to lift as thin sheets that redeposit on adjacent wafers and create particle defects. A pre-wet step of 60–90 seconds in warm DI water at 35–40 °C hydrates the crust and reduces the burst release of film fragments. In single-wafer spray tools, the same function is achieved by ramping chemical flow from 0.2 L/min to 1.0 L/min over the first 90 seconds. The dry film strip itself uses EKC-265 at 70 °C for 10–15 minutes on 40 µm films; endpoint is determined when reflected light intensity at 550 nm returns to the copper seed-layer baseline. Premature endpoint calls occur if the optical sensor is positioned near the wafer flat or panel edge, where lamination edge bead can be 5–10 µm thicker than the centre. The strip bath is followed by a 30-second hot DI water rinse at 55 °C and an isopropanol vapour dry at 80 °C. Post-strip defect detection uses laser scattering maps; the acceptance limit is 0.02 defects/cm² for an ISO 14644-1:2015 class 1000 cleanroom operation. Terminal products are fan-out packages with copper line widths of 10–20 µm.

For through-silicon via arrays with 10:1 aspect ratio and via depth of 50–100 µm, positive photoresist plugs are used to protect the via bottom during seed-layer etch. After etch, the resist plugs are removed in a two-bath EKC-265 line. The first bath is maintained at 65 °C with low-frequency ultrasonic agitation at 40 kHz to dislodge the hardened plug surface; the second bath is held at 75 °C with 1.0 MHz megasonic energy to remove residues inside the via. The strip time for 60 µm via plugs is 20–30 minutes; if the second bath is skipped, via-bottom residues remain in 20–40% of vias when inspected by cross-section SEM at 5 kV. Post-strip rinse uses sequential DI water at 20 °C and 60 °C to prevent thermal shock cracking of the thin oxide liner; a final vacuum-assisted drying step at 500 Pa removes water from high-aspect-ratio vias. Cleaned TSV wafers then move to barrier deposition and electrochemical copper filling. Organic residue in the via bottom correlates with copper void formation in the subsequent fill step. The final products are interposer wafers for high-bandwidth memory and logic stacking.