In front-end logic manufacturing, the silicon nitride spacer and contact etch stop layer are deposited in hot-wall LPCVD furnaces where wafer thermal budget, pattern loading, and step coverage on three-dimensional gate structures constrain the choice of silicon precursor. Electronic-grade disilane is introduced through a dual-gauge stainless steel manifold after dilution to 5.0% in helium and is mixed with ammonia at a flow ratio of Si₂H₆:NH₃ between 1:25 and 1:50. Deposition occurs at a total pressure of 0.3 Torr to 0.8 Torr and a substrate temperature of 550 °C to 650 °C, approximately 100 K to 150 K below the monosilane benchmark. In 300 mm batch furnaces, the lower thermal activation reduces the risk of transient enhanced diffusion in source/drain extensions, but it also shortens the mean residence time of the reactive gas front along the tube, requiring furnace zone temperatures to be trimmed by ±3 °C and pressure ramp rates limited to 0.1 Torr/min. The downstream production process is a batch LPCVD sequence: vertical or horizontal furnace boats holding 50 to 150 wafers are pre-heated under nitrogen, the disilane/ammonia gas mixture is injected through distributors, and an in-situ dry etch or purge step prevents powder accumulation on the tube walls. The silicon nitride film is used as a spacer and contact etch stop layer; the terminal product is a 300 mm logic or memory wafer at the front-end-of-line, before self-aligned contact metallization. Cleanroom compliance for wafer handling follows ISO 14644-1:2015 Class 3; gas delivery and abatement systems comply with SEMI S2 equipment safety guidelines and ANSI/ISA-84.00.01 for safety instrumented functions. Operational boundaries include an upper moisture limit of 1 ppmv in the helium dilution gas and a manifold purge requirement after each idle period exceeding 30 min; disilane must not be mixed with air or oxygen-containing lines because the material is pyrophoric at ambient temperature.

What Limits Precursor Saturation in High-Aspect-Ratio 3D NAND Silicon Nitride Liners?

Conformality loss in high-aspect-ratio 3D NAND dielectric liners is governed by precursor self-limiting adsorption on hydroxyl-terminated silicon oxide surfaces and by purge dynamics in structures with aspect ratios above 50:1. Disilane is used in plasma-enhanced atomic layer deposition processes as the silicon source for silicon nitride or silicon oxide liners because its lower decomposition threshold compared with monosilane enables saturation at substrate temperatures between 75 °C and 150 °C, where thermal decomposition of silane would be insufficient. In production-scale single-wafer ALD chambers, the precursor is delivered as a 5.0% mixture in helium through a heated line maintained above 60 °C to prevent condensation. The cycle sequence consists of a disilane pulse, an argon purge, an oxygen or nitrogen plasma step, and a second argon purge. Published data for disilane-specific PEALD on structures above 80:1 is limited; conformality below that threshold depends more on purge time than on precursor exposure dose.

In the PEALD silicon nitride liner process, the effective Si₂H₆:NH₃ pulse flow ratio is maintained between 1:8 and 1:20, and the plasma step uses a nitrogen-argon mixture at a total pressure of 0.5 Torr to 2.0 Torr. The downstream production process is integrated into multi-step sequences for 3D NAND wordline liners and DRAM capacitor dielectric interface layers; the terminal products are memory wafers with silicon nitride liners in three-dimensional NAND arrays and silicon oxide interface liners in stacked capacitor DRAM cells. Device reliability qualification follows JEDEC JESD22-A108 for bias-temperature stress testing, while cleanroom control follows ISO 14644-1:2015 Class 3 and equipment safety compliance follows SEMI S2. An operational boundary is the requirement to purge the reactor for at least 5 s between precursor and plasma steps; insufficient purge produces gas-phase particles and non-uniform silicon incorporation in the form of silicon-rich films that shift etch rate and dielectric constant.

Selective epitaxial growth of in situ boron-doped SiGe source/drain regions at the 3 nm node operates within a processing window where excessive wafer temperature causes germanium desorption and pattern loading, while insufficient temperature arrests crystalline growth on the exposed silicon surface. Disilane is delivered as a 1.0% mixture in hydrogen through a heated line to a single-wafer reduced-pressure chemical vapour deposition reactor; the gas ratio Si₂H₆:GeH₄:HCl:H₂ is typically maintained between 1:0.4:1.5:120 and 1:1.2:3.0:200 at a total pressure of 20 Torr to 80 Torr and a wafer temperature of 550 °C to 650 °C. The lower decomposition temperature of disilane compared with silane allows the process to avoid the 700 °C threshold at which boron diffusion and germanium surface segregation become difficult to control. Production-scale reactors require a separately controlled HCl etch step before the silicon source is introduced to remove native oxide from the recessed source/drain area; selectivity loss below 5 nm fin pitch is observed when the HCl flow ratio drops below 1.5, while excessive HCl causes facet erosion and silicon recess. The downstream process sequence is: recess etch, wet clean, pre-clean, selective SiGe epitaxy, in-situ boron doping, and post-epitaxial anneal. The terminal product is a FinFET or gate-all-around nanosheet wafer with fully strained SiGe source/drain regions before silicide contact formation. The manufacturing environment complies with ISO 14644-1:2015 Class 3; the epitaxy reactor and dopant gas delivery comply with SEMI S2, and reactor exhaust abatement is designed for hydrogen and hydrogen chloride mixtures. An operational boundary is the exclusion of oxygen above 10 ppbv in the hydrogen carrier gas, because silicon oxide formation at the growth interface produces stacking fault defects and increases contact resistance.

Flexible OLED Thin-Film Encapsulation Silicon Nitride: Barrier Defect Density and Stress Control

Barrier layer stacks in flexible organic light-emitting diode displays must maintain a water vapour transmission rate below 10⁻⁵ g/m²/day while bending through a radius of less than 2 mm without cracking. Disilane-based plasma-enhanced chemical vapour deposition is used to deposit silicon nitride at a substrate temperature of 80 °C to 120 °C, which is below the glass-transition limit of the polymer substrate and below the degradation threshold of the organic emissive layer. The gas feed ratio Si₂H₆:NH₃:Ar is maintained between 1:8:40 and 1:15:60, with a total pressure of 0.5 Torr to 1.5 Torr and RF power density between 0.20 W/cm² and 0.45 W/cm² at 13.56 MHz. The production process is sheet-fed or roll-to-roll PECVD on polyimide carrier glass; barrier stacks alternate between silicon nitride and organic or inorganic planarisation layers to lengthen the diffusion path for water vapour and to interrupt pinhole propagation. The terminal product is a flexible OLED display panel with thin-film encapsulation, used in foldable mobile devices and automotive displays. Compliance includes ISO 14644-1:2015 Class 5 for display frontplane processing and IEC 62341-1 for OLED environmental test definitions. The process window is bounded by a sharp increase in compressive stress when RF power exceeds 0.45 W/cm²; this stress produces delamination at the polyimide interface after 10,000 bending cycles. Conversely, at power density below 0.20 W/cm², film density declines below 2.3 g/cm³ and the moisture barrier fails during damp-heat testing at 85 °C/85% relative humidity.

When the Substrate Cannot Exceed 350°C: Disilane-Based Amorphous Silicon in TFT Backplanes

Under 350 °C, the amorphous silicon channel layer deposited by plasma-enhanced chemical vapour deposition in thin-film transistor backplanes requires a precursor that undergoes sufficient gas-phase dissociation at reduced thermal input. Disilane is injected into a multi-chamber PECVD platform at a dilution of 5.0% to 10.0% in helium or hydrogen and combined with hydrogen at a Si₂H₆:H₂ flow ratio of 1:20 to 1:50; deposition occurs at 250 °C to 350 °C, 1 Torr to 3 Torr, and RF power density between 0.05 W/cm² and 0.20 W/cm² at 13.56 MHz. The downstream process includes sequential deposition of gate dielectric, intrinsic amorphous silicon, n-type doped silicon, and source/drain metal on a glass substrate, followed by photolithography and reactive ion etching. The terminal product is a thin-film transistor backplane for LCD panels, organic light-emitting diode display pixel circuits, or medical X-ray flat panel detectors. Cleanroom compliance is ISO 14644-1:2015 Class 5; the PECVD system and gas cabinet comply with SEMI S2 and OSHA 29 CFR 1910.1200 hazard communication requirements. A process limitation appears when substrate temperature drops below 200 °C: hydrogen content in the amorphous silicon film rises above 15 at% and field-effect mobility falls below 0.5 cm²/Vs, making the backplane unsuitable for high-resolution displays. For disilane-specific mobility and threshold voltage stability data on large-area Gen 8.5 glass substrates, published data for this specific configuration is limited; equipment-specific characterisation is required before process transfer.