| HS Code | 486027 |
| Product | Dielectric Universal Polishing Slurry Electronic/EL Grade |
| Appearance | Milky white liquid |
| Color | White |
| Ph | 10.5 - 11.5 |
| Mean Particle Size | 80 - 120 nm |
| Solids Content | 30 - 32 % |
| Sio2 Concentration | 30 % |
| Density | 1.15 - 1.20 g/cm³ |
| Viscosity | 2.0 - 3.0 cP |
| Metal Impurities | < 1 ppm each (Na, K, Fe, Cu) |
| Chloride Content | < 10 ppm |
| Shelf Life | 6 months from date of manufacture |
| Storage Temperature | 0 - 30 °C |
As an accredited Dielectric Universal Polishing Slurry Electronic/EL Grade factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.
| Packing | Packaged in 5-gallon sealed pails with tamper-evident lids, labeled Electronic/EL Grade, ensuring cleanroom-safe handling and contamination-free delivery. |
| Container Loading (20′ FCL) | 20' FCL loaded with palletized drums of dielectric polishing slurry, secured and blocked for safe transport. |
| Shipping | This EL-grade dielectric polishing slurry ships in sealed, leak-proof containers via standard ground freight. It is generally not regulated as hazardous material, but requires careful handling to avoid spills or contamination. Temperature-controlled transit is recommended to prevent freezing or separation. Use proper labeling and secure packaging for safe, compliant delivery. |
| Storage | Store in tightly sealed original container in a clean, cool, dry, well-ventilated area. Protect from moisture, direct sunlight, and freezing temperatures. Keep away from incompatible chemicals, acids, or oxidizing agents. Do not expose to extreme heat. Avoid contamination when dispensing. Follow manufacturer’s shelf-life guidelines and ensure proper labeling. Use appropriate personal protective equipment when handling. |
| Shelf Life | Shelf life is 6 months from manufacture when stored sealed at controlled room temperature, away from light and freezing. |
On 300 mm front-end logic lines, the high-volume oxide CMP step that follows high-density plasma chemical vapor deposition silicon dioxide gap fill into etched silicon trenches is shallow trench isolation planarization. The dielectric universal polishing slurry, Electronic/EL Grade, is introduced onto a multi-platen rotary polisher equipped with a polyurethane pad of Shore D hardness 55–60, a 180 µm diamond pad conditioner, and closed-loop point-of-use blending. Industry compliance for this operation is governed by SEMI C1-1108 for cation and anion trace metals below 10 ppb for critical elements, SEMI F57-0316 for polymer contact in ultrapure water distribution, ISO 14644-1:2015 Class 3 for slurry preparation areas, ASTM D6919-17 for dissolved alkali and alkaline-earth cations in slurry filtrate, and REACH 1907/2006 Annex XVII for restricted hazardous components in the EU supply chain. The point-of-use addition ratio is 1:1 to 1:3 by volume slurry-to-18.2 MΩ·cm ultrapure water; after mixing, the working slurry has a colloidal abrasive concentration of 6–12 wt%, a pH of 10.5–11.5, and is recirculated at 20–23 °C through 0.1 µm absolute-rated filtration. Downstream production process parameters include downforce 2.5–4.0 psi, backpressure 1.0–2.0 psi, platen speed 60–110 rpm, carrier speed 55–100 rpm, and slurry flow 150–300 mL/min; the oxide removal rate typically ranges from 180–340 nm/min depending on dilution ratio, pad age, and condition of the 180 µm diamond conditioner. The polish stop is 10–30 nm of silicon nitride, with post-polish in-line ellipsometry monitoring oxide remaining at 50–120 nm over active area. Dishing and erosion are held below 30 nm and 15 nm, respectively, because excessive nitride loss shifts the active-area threshold voltage of the final device. End devices produced from this planarized layer include system-on-chip processors, graphics processing units, field-programmable gate arrays, and application-specific integrated circuits fabricated at 28 nm, 16 nm, 7 nm, and 5 nm FinFET nodes.
Copper dual damascene back-end-of-line dielectric CMP requires a pH window of 10.2–10.8 and a point-of-use dilution within 1:1 to 1:2 by volume with 18.2 MΩ·cm ultrapure water; higher dilution lowers abrasive concentration to 8–12 wt% and reduces shear-related low-k delamination but can increase within-wafer non-uniformity above 3.0% on 300 mm wafers. Industry compliance includes SEMI C1-1108 trace metal limits for sodium, potassium, iron, and copper below 5 ppb each, SEMI S2-0720a for exhaust and waste treatment on the CMP polisher, ISO 14644-1:2015 Class 3 for point-of-use blending enclosures, and REACH 1907/2006 for transportation and packaging documentation. The downstream production process uses a three-platen rotary CMP system: platen 1 for bulk copper removal with a copper-specific slurry, platen 2 for barrier layer removal, and platen 3 for dielectric touch-up with this universal slurry; final dielectric buff uses downforce 1.5–2.5 psi, platen speed 60–90 rpm, and slurry flow 120–250 mL/min. Post-polish cleaning uses dilute citric acid in the copper-compatible cleaning module, followed by brush scrubbing and spin-rinse drying. The slurry must not contain amine-based additives that can shift the surface zeta potential of the low-k film and increase k-value drift after 10,000 wafer passes; published data for specific low-k material interaction is limited, so each dielectric stack is qualified through k-value shift testing after extended polish cycles. Finished devices fabricated through this route include high-performance server CPUs, network switch ASICs, AI accelerator processors, and 2.5D/3D logic chiplets integrated on silicon interposers.
Because vertical NAND tier stacking alternates silicon nitride etch-stop layers and TEOS or HDP silicon oxide tiers, the oxide CMP step after each tier deposition must produce sub-2.5% within-wafer non-uniformity across a 300 mm wafer while preserving the nitride staircase. The universal dielectric slurry is point-of-use diluted 1:1 to 1:2 with 18.2 MΩ·cm ultrapure water; final abrasive solids are 8–14 wt%, pH is 10.5–11.2, and 0.05–0.15 wt% of a selectivity modifier is added only after on-tool qualification for the specific tier thickness. Industry compliance in this segment is driven by SEMI C1-1108 for trace metal contamination in memory-grade chemicals, SEMI F57-0316 for extractables from slurry distribution lines, ISO 14644-1:2015 Class 3 for the slurry distribution subsystem, and SEMI S2-0720a for polisher exhaust safety. Downstream production process: after each oxide tier deposition, a 300 mm multi-head CMP polisher removes 200–500 nm of oxide at 150–280 nm/min with downforce 2.0–3.5 psi, platen speed 70–110 rpm, slurry flow 180–320 mL/min, and in-situ pad conditioning with a 180 µm diamond disk at 0.5–1.5 lbf load. The process specification for the staircase region is a step height variation below 20 nm across 10 mm edge exclusion; the slurry must exhibit a silicon oxide-to-silicon nitride selectivity of at least 30:1 to avoid nitride break-through on the staircase edges. Post-CMP metrology uses spectroscopic ellipsometry and atomic force microscopy to monitor surface roughness Ra below 0.5 nm in the array and staircase regions. The resulting memory product stack is qualified for 176-layer, 232-layer, and 300-layer 3D NAND devices, enterprise solid-state drives, client SSDs, UFS 3.1/4.0 mobile storage, and embedded MultiMediaCard modules for automotive and industrial storage.
In 2.5D package lines where copper through-silicon vias are exposed by backside silicon etch, the remaining dielectric passivation layer must be planarized to leave copper protrusion of 2–10 nm and no surface oxide residue on 50–100 µm thinned wafers. The slurry is point-of-use mixed at 1:1 to 1:2 by volume with 18.2 MΩ·cm ultrapure water; the final colloidal abrasive concentration is 8–12 wt% and pH is held at 10.0–10.8, with no foaming surfactants because thin-wafer handling uses spin-coating and temporary bonding equipment sensitive to organic residues. Industry compliance is based on SEMI C1-1108 for trace metals below 10 ppb, SEMI S2-0720a for exhaust and interlocks on the polisher, ISO 14644-1:2015 Class 3 for post-thinning cleanroom operations, JEDEC JESD22-A104 for temperature cycling reliability of the final package, and REACH 1907/2006 Annex XVII for restricted substances in imported wafers. Downstream production process parameters: a 300 mm or 200 mm temporary bonded wafer carrier is polished on a single-side CMP tool with a hard polyurethane pad, downforce 1.5–3.0 psi, platen speed 40–80 rpm, slurry flow 100–200 mL/min, and 0.1 µm absolute filtration on the point-of-use line. The process must avoid over-polishing the silicon surface beneath the dielectric; an endpoint system using motor current or optical emission is set to stop when copper protrusion reaches 2–10 nm. Post-CMP cleaning uses an alkaline or neutral solution that does not etch the exposed copper vias. The final package formats produced from this step include high-bandwidth memory stacks, logic-on-interposer chiplets, 2.5D graphics processor packages, and silicon bridge interconnect devices used in datacenter AI modules.
A 1.0–2.0 µm LPCVD TEOS sacrificial oxide deposited over a patterned silicon device layer is planarized before the oxide release etch to produce flat structural layers and reduce subsequent vapor-phase HF release time. The dielectric slurry is diluted 1:3 by volume with 18.2 MΩ·cm ultrapure water to cap removal rate at 120–180 nm/min; final abrasive concentration is 4–6 wt% and pH is 9.5–10.5. Industry compliance for MEMS wafer fabs uses SEMI C1-1108 for mobile ion control, SEMI F57-0316 for fluid contact materials, ISO 14644-1:2015 Class 5 or better for MEMS CMP bays, and RoHS 2011/65/EU for lead-free terminal products. The downstream production process is run on 150 mm or 200 mm single-wafer CMP tools with a soft polyurethane pad, downforce 1.0–2.5 psi, platen speed 30–60 rpm, and slurry flow 80–150 mL/min; wafer bow after polishing is controlled by matching oxide removal across the wafer to within 2.0% and by using a sub-ambient pressure carrier to avoid edge roll-off in the sacrificial oxide. The slurry must not leave chloride or sulfur residues above the detection limit of ion chromatography after the post-polish rinse, because these anions poison the subsequent vapor-phase HF release etch and degrade AlSi metal contact resistance. Published data for this specific MEMS sacrificial oxide configuration is limited; qualification therefore includes release etch rate monitoring and residual stress measurement on 1,000-wafer split lots. Terminal product types include inertial measurement units, automotive pressure sensors, MEMS microphones, digital micromirror devices, and microbolometer arrays for thermal imaging.
For 200 mm silicon IGBT lines, the grown field oxide layer of 1.2–2.4 µm is planarized before polysilicon gate deposition to reduce step height at the active cell edge and improve photolithographic depth of focus. The slurry is point-of-use blended at 1:1 by volume with 18.2 MΩ·cm ultrapure water; final abrasive concentration is 10 wt%, pH is 11.0, and sodium and potassium concentrations are below 50 ppb to avoid mobile ion drift in gate oxide reliability tests. Industry compliance includes SEMI C1-1108 for trace metal purity, SEMI S2-0720a for polisher safety interlocks, ISO 14644-1:2015 Class 5 for power semiconductor front-end operations, and IEC 60747-9:2019 for insulated-gate bipolar transistor qualification. The downstream production process uses a 200 mm CMP polisher with a hard polyurethane pad, downforce 3.0–5.0 psi, platen speed 50–90 rpm, slurry flow 150–300 mL/min, and endpoint by motor current change at the thermal oxide-to-silicon nitride interface. Oxide removal rate is held at 200–350 nm/min; the slurry must provide a silicon oxide-to-silicon nitride selectivity of at least 40:1 because the nitride layer serves as both polish stop and subsequent hard mask. The process must not expose the underlying silicon substrate; remaining field oxide after CMP is controlled to 0.3–0.6 µm over the active cells, with less than 5% thickness non-uniformity across the wafer. The output power semiconductor components include 600 V, 1,200 V, and 1,700 V IGBT modules, fast-recovery diodes, automotive power modules, and silicon carbide power MOSFETs with a 1.0 µm TEOS inter-metal dielectric layer planarized in the same process flow.
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Dielectric Universal Polishing Slurry Electronic/EL Grade is an aqueous colloidal silica dispersion formulated for chemical-mechanical planarization of dielectric films in semiconductor interconnect fabrication. The product is not identified by a universal model number; manufacturer-specific catalog codes typically append a particle-size suffix to the base designation, and the Electronic/EL Grade label is a purity classification that must be cross-referenced to Section 1.1 of the safety data sheet when a purchase specification requires a model. The dispersion is stabilized in the alkaline range, with pH controlled between 9.8 and 11.2 as measured by ASTM E70. The abrasive phase is colloidal silica with a nominal secondary particle size of 65 nm to 90 nm by dynamic light scattering per ISO 22412:2017. Total solids content is controlled between 20 wt% and 30 wt%. Point-of-use filtration at 0.5 µm or 1.0 µm is recommended to remove agglomerates and reduce large-particle excursions. The material is intended for direct delivery through high-purity perfluoroalkoxy or polytetrafluoroethylene distribution loops without dilution.
Release documentation for Electronic/EL Grade slurries typically quantifies trace metal contamination below 100 ppb per element for Li, Na, Mg, Al, K, Ca, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Zr, Mo, Ag, Cd, Sn, Ba, and W when analyzed by inductively coupled plasma mass spectrometry following SEMI C43-0719 closed-vessel acid digestion. Anions such as chloride, nitrate, and sulfate are controlled below 1 ppm in filtered samples to reduce the risk of electrochemical corrosion on exposed copper lines at subsequent process steps. Large-particle counts for particles ≥0.5 µm are held below 50 particles/mL by single-particle optical sensing per SEMI C79. The alkaline pH remains below 11.5; therefore, the material is not classified as a corrosive transport hazard under most regulatory frameworks. Nevertheless, drum venting and cleanroom handling procedures must prevent carbon dioxide ingress, which lowers pH and can induce particle aggregation.
For semiconductor dielectric planarization, the Electronic/EL Grade label functions as a release envelope rather than a single parameter. It constrains cation contamination, particle-size distribution, zeta potential, and suspension conductivity to preserve removal-rate uniformity and defect density. Conductivity at 25 °C is maintained below 200 µS/cm by ion-exchange or ultrafiltration purification; higher ionic strength compresses the electrical double layer surrounding each colloidal silica particle and can raise the coefficient of variance of blanket oxide removal across a 300 mm wafer. Viscosity is measured at 25 °C with a Brookfield LV spindle at 60 rpm under ASTM D2196; release values between 1.5 mPa·s and 5.0 mPa·s are common for silica loadings in this range. Specific gravity at 25 °C is typically 1.08 to 1.15 when measured by a digital density meter calibrated against ASTM D4052.
Because mobile ions such as sodium and potassium affect threshold voltage stability in metal-oxide-semiconductor structures, Electronic/EL Grade slurries are packaged in acid-washed high-density polyethylene drums or fluoropolymer-lined totes. Filling is performed in semiconductor-grade cleanrooms, and the lot certificate of analysis includes actual trace-metal values rather than only pass/fail statements. Bulk deliveries may require dedicated tanker trailers with fluoropolymer linings and nitrogen blanketing to prevent airborne contamination. End users should verify that the point-of-use distribution system does not contain brass, stainless steel fittings with high sulfide inclusions, or elastomer seals that leach zinc, calcium, or sulfur. Regulatory classification is supplier-specific; process chemicals of this type are generally not within scope of RoHS 2011/65/EU, and REACH registration data are supplied in the extended safety data sheet.
The table below presents a representative release envelope derived from supplier technical bulletins for electronic-grade colloidal silica slurries. Values are not a substitute for lot-specific certificates of analysis, but they define the usual acceptance window for this product class.
| Parameter | Test method | Release envelope |
|---|---|---|
| pH | ASTM E70 | 9.8–11.2 |
| Mean particle size D50 | ISO 22412:2017 | 65 nm–90 nm |
| Total solids | Gravimetric desiccation at 105 °C | 20 wt%–30 wt% |
| Viscosity at 25 °C | ASTM D2196 | 1.5 mPa·s–5.0 mPa·s |
| Conductivity at 25 °C | ISO 7888 | <200 µS/cm |
| Large particle count ≥0.5 µm | SEMI C79 | <50 particles/mL |
| Trace metals, each element | SEMI C43-0719 | <100 ppb |
Total organic carbon is often specified below 50 ppm in the filtered slurry to limit bacterial growth in recirculation loops. If the distribution loop is idle for more than 24 h, low-level ultraviolet treatment or hydrogen peroxide addition is recommended by equipment suppliers to prevent microbial film formation on the point-of-use filter. However, any oxidizer addition must be validated because hydrogen peroxide above 0.1 wt% can modify surface silanol chemistry and shift oxide removal rate.
Particle-size distribution is multimodal in intensity-weighted dynamic light scattering. The span, defined as (D90−D10)/D50, is typically 0.4 to 0.7 for electronic-grade colloidal silica. A narrow span is required because agglomerates above 0.2 µm correlate with micro-scratch defect density on polished oxide surfaces. Zeta potential is measured by electrophoretic light scattering per ISO 13099-2:2012; at native pH the slurry maintains a zeta potential between −40 mV and −60 mV. This range provides sufficient electrostatic repulsion for colloidal stability without excessive ionic strength. Dilution with deionized water outside the resistivity range 10 MΩ·cm to 18 MΩ·cm may introduce divalent cations that compress the double layer and raise the aggregation rate.
Shear stability is evaluated by circulating the slurry through a bellows pump at 10 L/min for 24 h and re-measuring large particle counts. A pass criterion is a shift of less than 10 particles/mL at ≥0.5 µm after the test. Centrifugal pumping with high-speed mixed-flow impellers can create local shear rates above 10⁵ s⁻¹; this may fracture weak aggregates but also raises tank temperature and accelerates silica dissolution. Recirculation loops longer than 30 m should be designed with low-shear diaphragm or bellows pumps, and point-of-use polishing head pressure should not exceed 40 psi to avoid line fatigue and slurry drying at dead legs. Temperature of the loop should be controlled at 20 °C to 25 °C; excursions above 30 °C can increase particle dissolution and reduce abrasive life.
Batch-to-batch variance in particle-size D50 is held within ±5 nm across single manufacturing campaigns, based on supplier technical bulletins. The polishing removal rate may shift by 50 Å/min to 80 Å/min per 10 nm increase in D50 on blanket oxide under fixed downforce. Consequently, the slurry is blended in large homogenous lots, and point-of-use tanks are recirculated before process qualification. No on-site particle-size adjustment is recommended because dilution or pH adjustment invalidates the release envelope and can alter selectivity.
For production-scale integration, the slurry is delivered to a 300 mm CMP module with a 50 µm point-of-use filter, a peristaltic or bellows slurry pump, and an in-line flow meter calibrated at 100 mL/min to 250 mL/min. Polishing is performed on a rotary or orbital polisher with a polyurethane pad. Downforce is held between 3 psi and 4 psi for blanket oxide and between 2 psi and 3 psi for fragile low-k films. Platen velocity of 60 rpm to 90 rpm and a slurry flow of 150 mL/min are typical starting points for product qualification. Under these conditions, supplier application notes for silica-based universal dielectric slurries report blanket PECVD silicon dioxide removal rates of 400 Å/min to 600 Å/min when measured by spectroscopic ellipsometry with a 49-point polar map on 300 mm wafers. Published data for this specific Electronic/EL Grade configuration is limited; site-specific requalification remains necessary because removal rate shifts with pad conditioning, chamber temperature, wafer manufacturer films, and polishing head geometry.
Silicon nitride removal rates are typically 150 Å/min to 250 Å/min under the same downforce, producing an oxide-to-nitride selectivity of approximately 2:1 to 4:1. This selectivity window permits the slurry to serve as a single consumable when a nitride layer acts as a polish stop. For cobalt and copper cap structures, the slurry is not recommended for direct high-pressure planarization after metal exposure because alkaline silica chemistry can generate metal contamination and organic residues. Dedicated metal-polish slurries with benzotriazole passivation and lower pH are necessary after copper or cobalt is revealed. The universal grade is therefore restricted to dielectric stages before barrier metal exposure or to structures where the stop layer is silicon nitride or a non-conductive etch-stop dielectric.
End-point detection for dielectric CMP using this slurry is generally based on optical reflectance or motor-torque change. The optical endpoint window is reduced when polishing oxide over nitride because the removal-rate contrast between films is smaller than for dedicated oxide slurries. Production lines with endpoint algorithms calibrated for high-selectivity oxide slurries may require re-optimization of trigger thresholds and polish time limits. The use of a platen flush after endpoint reduces residual slurry defects; a 10 s to 20 s deionized water flush at 100 mL/min is typical before pad conditioning.
In multi-step interconnect integration, dedicated oxide slurries are typically optimized to maximize silicon dioxide removal with low defectivity, while dedicated nitride slurries are formulated to remove silicon nitride selectively or to stop on nitride. The universal Electronic/EL Grade occupies an intermediate design point. Its colloidal silica loading of 20 wt% to 30 wt% is lower than some high-rate oxide slurries supplied above 30 wt% solids according to their safety data sheets. Consequently, shallow trench isolation oxide polish may require a longer polish time or higher platen speed to reach the same final thickness. In contrast, the pH range of 9.8 to 11.2 produces an oxide-to-nitride selectivity suitable for shallow trench isolation structures that use nitride as a hard mask.
The principal difference from fumed silica slurries is particle architecture. Colloidal silica particles are discrete, spherical, and produced by aqueous nucleation; fumed silica consists of chain-like aggregates that retain angular morphology even after high-shear dispersion. Defect scans using a KLA SP2 with a 0.2 µm threshold typically show lower scratch counts for colloidal silica than for fumed silica at equivalent blanket oxide removal rate, while fumed silica can achieve higher blanket oxide removal above 600 Å/min under the same 3 psi to 4 psi downforce. Ceria-based dielectric slurries differ in removal mechanism: ceria offers high oxide-to-nitride selectivity and blanket oxide removal rates that can exceed 1000 Å/min at 3 psi, but post-polish cleaning requires cerium-specific chemistries and the abrasive may leave metallic cerium residues. The silica-based Electronic/EL Grade avoids cerium residue and is compatible with dilute ammonium hydroxide post-polish cleaning at 25 °C to 40 °C.
Compared with application-specific oxide and nitride slurries, the universal grade reduces changeover time and inventory, but it does not maximize removal rate or minimize defectivity for any single film. A production line that uses two dedicated slurries may achieve a 10% to 20% reduction in total polish time on a multi-step process at the cost of separate blend, filter, and waste routing. The universal grade is selected when process integration simplicity outweighs film-specific performance. The cost per wafer calculation must include pad wear, post-polish cleaning chemistry, endpoint detection consistency, and waste neutralization; slurry price alone is an incomplete discriminator.
Carbon-doped oxide dielectrics with porosity above 20 % present a process conflict: the alkaline slurry can penetrate open pores, alter the dielectric constant, and leave silanol or organic residue after cleaning. Because the universal grade is optimized for oxide and nitride, its direct use on unsealed porous low-k films is limited to short buffing cycles at downforce below 2 psi and platen speed below 60 rpm. Pore sealing by plasma-enhanced chemical vapor deposition of a thin oxide or by UV-cure densification is required before high-pressure planarization. Dielectric constant shift after polishing is monitored by capacitance-voltage measurement on metal-insulator-semiconductor capacitors using an LCR meter at 100 kHz; a shift of more than 0.2 units indicates slurry intrusion and requires process modification.
For integration schemes with air gap structures or highly porous sacrificial films, published data for this specific slurry configuration is limited. The universal dielectric slurry is not a drop-in replacement for low-k-specific chemistries that are formulated at near-neutral pH. The user is directed to short-loop patterned wafer qualification before committing to a manufacturing process flow. Adhesion loss and film shrinkage should be assessed by scanning electron microscopy cross sections after 30 s and 60 s over-polish intervals to determine the safe over-polish margin.
Storage conditions impose additional constraints. The slurry must be kept between 5 °C and 35 °C; freezing destroys the dispersion because ice crystal growth ruptures the electrical double layer and produces irreversible sedimentation. Agitation or recirculation every 24 h is required in tanks to prevent solids settling. Shelf life from the date of manufacture is typically 12 months in sealed containers, but point-of-use loop ageing can reduce practical life to 3 months if the loop is not flushed daily. The material is incompatible with acidified lines, strong oxidizers, and cationic flocculants; co-feeding with previously used acidic slurry without a flush can form gel deposits in manifolds. No claim of compatibility with all pad types is made; pad manufacturers’ approved slurry lists and extractable studies should be consulted before changing pad lot or supplier.
