| HS Code | 407571 |
| Product Type | Deep trench silicon dioxide etchant, Electronic/EL Grade |
| Chemical Family | Buffered hydrofluoric acid solution |
| Active Ingredients | Ammonium fluoride and hydrofluoric acid |
| Appearance | Clear colorless liquid |
| Specific Gravity | 1.12 at 25°C |
| Ph | 4.0 to 5.0 |
| Hf Content | 6.0% by weight |
| Nh4f Content | 30.0% by weight |
| Etch Rate On Thermal Sio2 | 0.15 to 0.30 µm/min at 25°C |
| Selectivity To Silicon | Greater than 100:1 |
| Solubility In Water | Fully miscible |
| Storage Temperature | 20 to 25°C |
| Shelf Life | 6 months from date of manufacture |
| Metal Impurities | Each element less than 1 ppm |
As an accredited Deep trench silicon dioxide etchant Electronic/EL Grade factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.
| Packing | Deep trench silicon dioxide etchant, Electronic/EL Grade, supplied in sealed 4-liter bottles for high-purity semiconductor processing. |
| Container Loading (20′ FCL) | 20′ FCL: Deep trench silicon dioxide etchant (Electronic/EL Grade) loaded in sealed drums, safely secured, fully compliant for transport. |
| Shipping | Deep trench silicon dioxide etchant (Electronic/EL Grade) ships as a corrosive, high-purity chemical. It must be packaged in sealed HDPE containers with UN-rated hazardous labels and provided with safety documentation. Transport requires controlled temperature, secure upright loading, and compliance with applicable air/ground regulations to prevent leakage or contamination. |
| Storage | Store in original tightly sealed containers under clean, dry, well-ventilated conditions. Maintain stable, moderate temperature away from heat, sunlight, and moisture. Electronic/EL Grade requires strict contamination control; use dedicated, corrosion-resistant packaging. Keep separate from incompatible substances, especially metals, bases, and oxidizers. Inspect containers regularly and follow semiconductor-grade handling protocols to preserve purity and stability. |
| Shelf Life | Shelf life is typically one year from manufacture date when stored unopened in the original container at controlled room temperature. |
In 3D NAND flash production, the high-aspect-ratio channel hole is dry-etched through an alternating silicon dioxide and silicon nitride tier stack; the process leaves a fluorocarbon-polymer-modified silicon dioxide sidewall and a native oxide layer at the exposed silicon bottom. Before selective silicon epitaxial growth at the channel bottom, an electronic/EL grade deep trench silicon dioxide etchant is diluted with ultra-pure water to a final concentrate-to-water ratio of 1:100 and dispensed through a 0.05 µm point-of-use filter in a 300 mm batch immersion tool. The bath is held at 23 °C ± 0.5 °C; under these conditions the thermal silicon dioxide etch rate is limited to 2–4 nm/min, while silicon nitride loss remains below 0.1 nm/min. Replenishment is controlled by conductivity and specific gravity feedback, with 0.5–1.0 vol% concentrate added per wafer lot to maintain fluoride activity after drag-out and evaporation. Metallic impurity limits for Fe, Cu, and Ni are constrained by SEMI C7 Grade 2 to ≤ 0.5 ppb each; particle counts at 0.09 µm are maintained below 20 particles/mL. On production lines, over-etch beyond 30% of the endpoint time produces bottom silicon pitting deeper than 5 nm and increases contact resistance at the epitaxial interface. Inspection is performed by inline XPS or ToF-SIMS on monitor wafers after each bath change. Terminal finished products are 3D NAND memory dies with 96 to 232 wordline layers.
| Control item | Limit | Standard designation |
|---|---|---|
| Metal impurities, Fe/Cu/Ni | ≤ 0.5 ppb each | SEMI C7 Grade 2 |
| Particle count above 0.09 µm | ≤ 20 particles/mL | SEMI C7 / laser particle counter |
| Ultra-pure water resistivity | ≥ 18.2 MΩ·cm | ASTM D5127-13 |
| Cleanroom air cleanliness | Class 3 | ISO 14644-1:2015 |
For DRAM deep-trench capacitor arrays with trench aspect ratios above 40:1, the as-etched silicon trench is lined with sacrificial silicon dioxide that must be removed before ONO node dielectric deposition. The etch bath uses a buffered hydrofluoric acid formulation with an ammonium fluoride-to-hydrofluoric acid addition ratio of 10:1 by volume, where the ammonium fluoride component is 40 wt% aqueous NH4F and the hydrofluoric acid component is 49 wt% HF. The mixture is diluted to 70% strength with ultra-pure water at initial fill; subsequent replenishment adds 0.3–0.6 L of concentrate per 25-wafer lot in a PVDF-lined recirculating wet bench with Teflon immersion heaters. At 22 °C ± 0.3 °C, the thermal silicon dioxide etch rate is held to 6–9 nm/min, and the silicon etch rate is suppressed by the buffered fluoride chemistry. The bath is dumped when total silicon dissolution exceeds 500 mg/L because dissolved silicon creates micromasking defects on the trench upper sidewall. Metallic impurity requirements follow SEMI C7 for hydrofluoric acid and SEMI C1 for sampling; cleanroom air quality at the tank is controlled to ISO 14644-1:2015 Class 3. Over-etch beyond 120% of endpoint time has been observed on inline SEM to produce bowl-shaped widening of the upper 100 nm of the trench by 4–6 nm, compromising capacitor capacitance uniformity. Terminal finished products are DRAM memory dies in the 1α-nm to 1γ-nm node range.
Power discrete fabrication requires sacrificial silicon dioxide removal after deep trench plasma etching and before gate oxidation in trench-gate IGBT and MOSFET flows. The etchant is mixed at a formulation addition ratio of 7:1 NH4F/HF and is processed at 18 °C ± 0.5 °C in a nitrogen-purged single-wafer spray processor. The lower temperature places the thermal silicon dioxide etch rate at 15–20 nm/min and reduces the isotropic undercut at the hard mask edge, which is a failure mode when the bath exceeds 23 °C. Time-based termination is used because the sacrificial damage layer is too thin for optical endpoint detection; each wafer is processed with a 0.2 mL/L spike of 49% HF to counteract fluoride depletion. Metallic cation impurities are held to Fe ≤ 0.5 ppb, Cu ≤ 0.5 ppb, and Ni ≤ 0.3 ppb as measured by ICP-MS and compliant with SEMI C7 Grade 3 limits. On production lines, a 5 °C upward drift increases the trench top critical dimension by 8–12 nm, causing gate oxide thinning at the trench corner. Rinsing is performed with ultra-pure water followed by isopropyl alcohol vapor drying to reduce particle counts on vertical sidewalls. Terminal finished products are trench-gate IGBT dice for automotive power modules.
Backside illuminated CMOS image sensor wafers use deep trench isolation structures filled with plasma-enhanced silicon dioxide. After chemical mechanical planarization, a controlled oxide recess is carried out with the electronic/EL grade deep trench silicon dioxide etchant diluted at a formulation addition ratio of 1:20 concentrate to ultra-pure water in a megasonic immersion tank at 20 °C ± 0.3 °C. The resulting oxide etch rate is 1.5–2.5 nm/min, allowing a controlled recess of 100–200 nm across the wafer. Megasonic agitation at 900 kHz reduces particle accumulation on the high-aspect-ratio trench openings. The bath is spiked with 0.05–0.1 vol% of a non-ionic wetting agent to promote trench penetration; the additive is excluded when metal contamination above 1 ppb is detected by ICP-MS. Over-etch above 20% of the target recess increases silicon surface microroughness from 0.2 nm RMS to 0.5 nm RMS, which corresponds to elevated dark current in the finished device. Compliance for metal impurities and particle control is anchored to SEMI C7 Grade 2 and ISO 14644-1:2015 Class 3. Terminal finished products are BSI CMOS image sensor wafers for mobile and automotive camera modules.
Through-silicon via formation for advanced packaging deposits a TEOS silicon dioxide liner on the via sidewall and bottom. The electronic-grade deep trench silicon dioxide etchant is dispensed in a single-wafer spin tool at 15–30 rpm after dilution to 1:50 concentrate-to-water; a fluorosurfactant is added at 0.5–1.0 vol% to wet vias with 50 µm diameter and 200 µm depth without air bubble entrainment. The oxide removal rate is maintained below 5 nm/min to avoid undercutting the TEOS liner at the silicon/liner interface, and the dispense is time-modulated to prevent accumulation at the via bottom. After etching, the wafer is rinsed with ultra-pure water and dried with nitrogen to minimize water marks in high-aspect-ratio features. Cross-section SEM verification is performed on 50-wafer sampling intervals; production-scale batch-to-batch variance in oxide removal rate is below 0.3 nm/min when viscosity and surfactant concentration are controlled. Compliance includes SEMI C7 for metal impurity limits and REACH for hydrofluoric acid handling. Terminal finished products are silicon interposers and 3D-stacked packages for high-performance computing modules.
In MEMS inertial sensor and micro-actuator fabrication, wet sacrificial silicon dioxide removal from deep silicon trenches is selected when the sacrificial layer is thick enough that vapour HF throughput is insufficient or when the device structure is incompatible with ammonium fluoride residues. The process uses a 5:1 NH4F/HF formulation at 21 °C ± 0.5 °C, with 0.02–0.05 wt% non-ionic surfactant added to reduce surface tension during drying. Etch rates are 80–120 nm/min for phosphosilicate glass and 60–80 nm/min for thermal silicon dioxide, providing acceptable selectivity to doped silicon trenches. After etching, the wafers are displaced into isopropyl alcohol and dried with low-surface-tension vapour to prevent stiction, which is a dominant yield failure when oxide is removed from high-aspect-ratio trench arrays. Metallic impurities are controlled below 1 ppb for transition metals by monitoring with ICP-MS; compliance follows SEMI C1 and ISO 14644-1:2015 Class 3 at the wet-bench interface. Terminal finished products are hermetically sealed MEMS inertial sensor wafers and micro-actuator wafers for automotive and industrial sensor modules.
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Deep trench silicon dioxide etchant, Electronic/EL Grade, is supplied as an aqueous ammonium fluoride–hydrofluoric acid buffered etchant for controlled removal of thermal silicon dioxide in high-aspect-ratio trench capacitor and isolation structures. The product designation DT-EL-7:1 denotes a 7:1 volumetric ratio of 40.0% NH4F to 49.0% HF, with 6:1, 10:1, and 14:1 ratios available for lower or higher silicon dioxide selectivity. The Electronic/EL Grade differs from general-purpose BOE by the use of semiconductor-grade raw materials, final filtration through a 0.2 µm fluoropolymer membrane, and lot-specific release testing for transition metal, alkali metal, anion, and particle burdens. The liquid is supplied in fluoropolymer drums of 20 L and 200 L, with wetted surfaces limited to high-density polyethylene, perfluoroalkoxy alkane, and polytetrafluoroethylene.
In the buffered fluoride system, the reactive etch path is dominated by HF2− and F− activity rather than by free HF concentration alone. The addition of NH4F at a 7:1 ratio shifts the equilibrium toward HF2−, reducing free HF activity and limiting photoresist attack while maintaining a thermal oxide etch rate suitable for recess depths of 50–200 nm. The pH buffering also slows the formation of insoluble ammonium hexafluorosilicate particles during bath aging. Dilute HF has a rising pH trajectory and a sharper etch-rate dependence on dissolved silicon in the bath, which makes it less suited to repeated dispense without real-time bath monitoring.
The difference is primarily in the flat-line trace metal budget and particle clearance, not in the silicon dioxide etch chemistry. A representative release certificate for the Electronic/EL Grade specifies individual transition metals at ≤ 1 ppb, total cation impurities at ≤ 10 ppb, chloride/nitrate/sulfate at ≤ 1 ppm, and particles ≥ 0.5 µm at ≤ 10 counts/mL. General-purpose BOE grades used in photovoltaic texturing or MEMS release typically tolerate transition metal levels of 10–100 ppb and particle counts one to two orders of magnitude higher. Both products remove thermal silicon dioxide by the sequence SiO2 + 4 HF → SiF4 + 2 H2O, followed by hydrolysis of SiF4 to H2SiF6 in aqueous media; the NH4F buffer stabilizes HF2− activity and retards pH drift. The Electronic/EL Grade controls metal ions that can deposit at the silicon–silicon dioxide interface and degrade the trench capacitor leakage floor.
| Parameter | Electronic/EL Grade release limit | General-purpose BOE typical range | Test method |
|---|---|---|---|
| Individual transition metals (Cr, Cu, Fe, Ni, Zn) | ≤ 1 ppb each | 10–100 ppb each | ICP-MS, SEMI C7/SEMI C8 |
| Total cation impurities | ≤ 10 ppb | 100–500 ppb | ICP-MS after acid evaporation, SEMI C7 |
| Chloride/nitrate/sulfate | ≤ 1 ppm | 5–20 ppm | Ion chromatography, ASTM D4327 |
| Particles ≥ 0.5 µm | ≤ 10 counts/mL | 50–500 counts/mL | Laser particle counting at 0.5 µm |
| Dissolved silicon after 7-day storage | ≤ 2 ppm | Not controlled | ICP-OES |
The flat-line impurity specification also has a direct process consequence in high-density circuits. When a general-purpose etchant is used for deep trench processing, the transition metal load can produce mid-gap recombination sites after the next thermal oxidation or annealing step. This is especially critical for capacitor trench sidewalls, where the silicon surface is not sacrificial and the trench sidewall acts as an active junction. The Electronic/EL Grade is therefore not simply a filtered version of standard BOE; the raw ammonium fluoride and hydrofluoric acid are selected from dedicated semiconductor-certified feeds, and the final blend is not reprocessed from returned material.
For high-aspect-ratio deep trench structures with top critical dimension below 110 nm and aspect ratio above 20:1, the etchant is dispensed through a point-of-use 0.1 µm filter onto a 300 mm single-wafer spin tool. Wafer rotation is maintained at 800–1,500 rpm, and the liquid temperature is held at 25.0 ± 0.5 °C by an inert heat exchanger. Recirculation is not recommended: bath aging increases dissolved silicon and ammonium hexafluorosilicate, which suppresses the etch rate and can leave sub-visible residue at the trench mouth. Production data from single-wafer tools indicate that the most frequent lot-to-lot variation source is not raw-material assay but evaporative ammonia loss from open dispense vessels, which raises pH and reduces etch-rate stability; closed pressure dispense systems with nitrogen-blanketed reservoirs reduce this drift.
The dominant failure mode on production single-wafer tools is particle contamination at the dispense nozzle after idle periods, not etch-rate shift. Dried ammonium fluoride crystals form at the nozzle–air interface when the tool is idle for more than 30 minutes; the crystal mass then becomes a local source of particle counts ≥ 0.5 µm on the next lot. Preventive maintenance includes a timed dispense of high-purity deionized water at idle intervals of 15 minutes and nozzle position verification after each preventive maintenance cycle. The same contamination mechanism is why recirculated etchant lines must be sloped and drained rather than left static.
The Electronic/EL Grade is delivered surfactant-free to avoid organic residue that would alter the leakage performance of high-k dielectric films on trench sidewalls. When wetting is limited, the first process adjustments are dispense pressure, rotation speed, or addition of a pre-wet rinse; organic surfactants or solvent co-solvents are excluded from the formulation. The surface tension of the as-supplied product is governed principally by the aqueous electrolyte matrix, and spray processing remains applicable for feature sizes above 45 nm. Below that feature size, the process window tightens, and published data for this specific configuration is limited. If lower surface tension is required, the recommended route is a separate sequential wetting step with a volatile halogenated solvent, not modification of the etchant composition.
For trench geometries with aspect ratio above 30:1, the dispense step is often split into three low-volume puddles with short spin intervals rather than a continuous stream. This reduces the liquid residence time at the trench mouth and prevents etch-rate suppression at the bottom of the trench from dissolved silicon carryover. The process is monitored by inline conductivity sensors downstream of the dispense nozzle; when conductivity drops by more than 2% from the fresh-etchant setpoint, the dispense module is switched to a fresh container. This switch point is derived from the bath-age curve rather than from elapsed time alone.
Wetted materials for storage and dispense are restricted to high-density polyethylene, polypropylene, perfluoroalkoxy alkane, and polytetrafluoroethylene. The etchant attacks borosilicate glass, fused quartz, silicon nitride, and titanium nitride; it must not be stored in containers with aluminum, stainless steel, or polycarbonate components. Storage is conducted in vented fluoropolymer drums at 15–25 °C, and the product has a retest interval of 12 months from the date of manufacture when kept under nitrogen blanket. At relative humidity above 60%, loading lines should be purged before connection to prevent condensation-derived particle transfer from the container mouth into the dispense module. Combining the etchant with ammonia or amine-based strippers in waste drains generates exothermic neutralization and may release HF vapor; separate drain lines are required.
The product is shipped with a Certificate of Analysis listing lot number, fill date, retest date, assay, particle count, and trace metal panel. A lot that fails the particle or metal specification is not reworked; the entire fill line is flushed with ultrapure water and dried with filtered nitrogen before the next batch is introduced. This containment protocol is part of the release workflow under ISO 9001:2015 and is audited by semiconductor customers during source qualification.
Thermal oxide etch rate for the 7:1 formulation is typically 85–110 nm/min at 25.0 ± 0.5 °C on 100 nm thermal oxide monitor wafers, measured by spectroscopic ellipsometry after 60 s dispense. The 10:1 dilution reduces the etch rate to approximately 55–75 nm/min; the 6:1 ratio raises the rate to 110–135 nm/min. Concentrated 49% HF etches thermal silicon dioxide at 180–240 nm/min under the same temperature control but lacks the buffering capacity required for uniform deep trench sidewall clearing. Table 2 summarizes the dilution window for target-film removal.
| Etchant system | Thermal SiO2 etch rate at 25.0 ± 0.5 °C | Typical process note |
|---|---|---|
| DT-EL-7:1 | 85–110 nm/min | Deep trench buffered etch |
| DT-EL-10:1 | 55–75 nm/min | Lower undercut |
| DT-EL-6:1 | 110–135 nm/min | Faster blanket recess |
| HF 49% | 180–240 nm/min | High etch rate, low buffer |
These rates are for densified thermal oxide; chemical vapor deposited oxide etches faster depending on film density and silanol content. Selectivity to silicon nitride is batch-dependent and must be re-qualified on the target film stack because published data for this specific formulation is limited. The etch-rate temperature coefficient is approximately 5–8% per °C in the 20–30 °C window, which is why the dispense temperature dead band is set to ± 0.5 °C for sub-10 nm trench liner recess.
Bath-age control is performed by spiking a known mass of thermal oxide monitor wafer into a small etchant sample and measuring the time to clear, then converting to etch rate. The endpoint is determined visually on pilot lines, but production tools use spectroscopic ellipsometry on a monitor wafer after the etch step. The bath-age curve is nonlinear: after approximately 12% of the fluoride inventory has been consumed as hexafluorosilicate, the etch rate falls off more rapidly. The point at which the etch rate falls below 80% of the fresh-bath value is used as the reject criterion.
Trace-metal release limits are not only analytical targets; they directly affect the data retention margin of trench capacitor cells. Copper and iron at the 1 ppb threshold can be reconcentrated at the wafer surface during spin drying, especially when the dispense module uses stainless steel tubing upstream of the point-of-use filter. The Electronic/EL Grade addresses this by requiring all wetted surfaces downstream of the final filter to be high-density polyethylene or perfluoroalkoxy alkane. Post-shipment cation contamination is monitored by ICP-MS after tenfold preconcentration; each lot is released only when the critical transition metal load remains within the upper limit specified in Table 1. Because the final rinse uses ultrapure water with total organic carbon below 5 ppb, any organic contamination contribution from the etchant package is also limited by the high-density polyethylene liner and the fluoropolymer closure.
Compared with anhydrous vapor-phase HF etching, the Electronic/EL Grade provides selectivity to thermal silicon dioxide over silicon and remains compatible with single-wafer spray processing at ambient pressure. Compared with dilute HF mixtures designed for native oxide removal, the 7:1 buffered system sustains higher fluoride activity for hardmask reflow and deep trench liner recess without the severe photoresist attack associated with concentrated HF. It also differs from conventional BOE in packaging integrity: the Electronic/EL Grade is filled under ISO 14644-1 Class 4 cleanroom conditions, with the container and blanketing gas tested for moisture and oxygen ingress before release. Quality management is maintained under ISO 9001:2015, and analytical methods follow SEMI C7 and SEMI C8 for assay and trace metals.
