On a 300 mm logic production line, cobalt metal polishing slurry is evaluated for middle-of-line contact integration when tungsten fill no longer meets line resistance at contact diameters below 20 nm. The electronic/EL grade is specified with low total trace metal contamination, because residual sodium, potassium, and iron degrade dielectric reliability after anneal. Cobalt is deposited by CVD or ALD into high-aspect-ratio contact holes lined with Ti/TiN or TiN, leaving an overburden that depends on deposition thickness and contact depth. The polishing step must remove this overburden while preserving the underlying barrier and adjacent low-k dielectric. The selectivity relationship is not linear. Cobalt removal in an oxidizer-containing slurry proceeds by surface oxidation, complexation of oxidized species, and mechanical removal by pad abrasion, while TiN removal is driven by the same oxidative chemistry at a different rate. If the pH and complexing agent concentration are not matched to the deposited cobalt film grain structure, a bimodal removal response emerges. The wafer edge can clear before the center or the center can clear before the edge. The resulting contact plug height variation appears as a broad distribution in single-contact Kelvin resistance. Process development uses a four-zone membrane carrier on a 300 mm rotary CMP platform. Endpoint control is based on platen torque and optical thickness where a stop layer is present. The endpoint algorithm must recognize the coefficient of friction transition as cobalt clears, otherwise the wafer edge loses contact plug height. The failure signature is not shorting but an increase in contact resistance variance. Slurry metrology before point of use includes particle size distribution by ISO 13320-1:2020, zeta potential by ISO 13099-1:2012, viscosity by ASTM D2196-20, and large particle count by ASTM E2490-08. Cleanroom handling follows ISO 14644-1:2015 Class 5 or stricter at dispense.

Why Does Cobalt Liner Over-Polish Corrode Copper Lines in Dual-Damascene Interconnects?

A cobalt liner/cap step in copper dual-damascene integration introduces a galvanic couple that does not exist in tungsten plug flow. Cobalt is deposited as a seed enhancement liner or as a selective cap to suppress electromigration. After cap deposition, the barrier CMP step removes residual cobalt and underlying TaN/Ta barrier from the dielectric without corroding copper lines. The electrochemical potential difference between cobalt and copper in the presence of an oxidizer creates a galvanic couple, so the slurry requires a synthetic corrosion inhibitor and controlled dissolved oxygen. Without inhibitor, copper pitting occurs along the dielectric sidewall. With too much inhibitor, the cobalt removal rate collapses and residual metal remains on the dielectric, reducing line-to-line breakdown margin. The process window is defined by pad type, platen speed, and slurry flow rate; on a 300 mm polisher the edge of the wafer is most sensitive because slurry residence time and pad temperature are highest there. Process control uses post-CMP scanning electron microscopy and resistivity measurement of serpentine/comb structures with line spacing below 40 nm. The acceptance criterion is not a single removal rate but a selectivity ratio that must be validated for each incoming cobalt cap thickness. Corrosion failure is observed as dark-field inspection defects along copper lines after CMP. These defects correlate with residual slurry oxidizer after rinse. The post-CMP cleaning sequence therefore involves a dilute organic acid rinse, followed by an alkaline rinse if compatible with the low-k dielectric, then deionized water meeting ASTM D1193-06. The exact sequence is constrained by the cobalt cap electrochemical stability and the dielectric damage limit. Published data for a specific slurry composition is limited; on production lines the clean recipe is tuned with electrochemical impedance spectroscopy of the copper/cobalt couple. The CMP step is inseparable from the cleaning module.

After electrochemical fill of cobalt into high-aspect-ratio silicon vias, two separate polishing operations are applied in 3D integration. The front-side operation removes thick cobalt overburden immediately after fill. The backside operation reveals cobalt vias after wafer thinning and dry etching of silicon. These operations have different selectivity requirements. Front-side polishing must remove overburden without damaging dielectric passivation. Backside polishing must stop on oxide and then clear silicon without exposing the via sidewall to smearing. The mechanical properties of cobalt cause ductile smearing when pad conditioning is insufficient; sub-surface damage propagates into the via structure. Slurry filtration at point of use is necessary to prevent large particles from creating scratches on exposed cobalt. On a 300 mm temporary carrier line, the wafer is thinned to 50 µm or less, so edge chipping and carrier-induced warp become dominant. The CMP recipe uses lower downforce than front-side overburden removal to avoid fracture. Via protrusion height after reveal is monitored because protrusion above the silicon surface interferes with hybrid bonding alignment. This measurement is taken with atomic force microscopy and cross-sectional scanning electron microscopy. The backside reveal step requires a debonding-compatible temporary adhesive; no universal standard exists for cobalt via reveal, so the cleanroom bond/debond module is maintained at ISO 14644-1:2015 Class 5 or stricter at dispense.

Mapping the Process Window for CoFeB Magnetic Tunnel Junction Planarization

MRAM stacks contain cobalt-rich ferromagnetic layers, typically CoFeB, separated by MgO. CMP is used to planarize bottom electrode and hard mask topography before tunnel barrier deposition or to remove interconnect overburden without disturbing the magnetic dead layer. The process window is extremely narrow. The cobalt removal rate must be low enough to avoid thinning the ferromagnetic layer, because magnetic anisotropy and tunnel magnetoresistance depend on the thickness of the CoFeB layer. Removal rate in an oxidizer-containing slurry can also oxidize the cobalt-rich surface and increase the magnetic dead layer. Published data for this specific configuration is limited. The available literature indicates that slurry pH and oxide abrasives with low particle size and narrow distribution are preferred to minimize scratching; however, universal formulations are not established. Endpoint control on these thin films cannot rely on friction change alone, because the total removal is often less than 10 nm. Optical endpoint or material-specific eddy current may not resolve such a thin remaining film. Therefore, removal is often controlled by timed polish on witness wafers, with magnetic measurement used to confirm film integrity. The acceptance parameters include areal surface roughness by atomic force microscopy according to ISO 25178-2:2012 and tunneling magnetoresistance ratio after a subsequent annealing step. One production-scale failure mode is the formation of sub-oxide residue on the MgO surface after planarization. The cobalt slurry oxidizer can diffuse through pinholes in the MgO and oxidize the lower ferromagnetic electrode. This effect appears as a decrease in tunneling magnetoresistance after annealing. The solution is to split the process into a short low-oxidizer polish, followed by a cleaning step that removes adsorbed metal ions. The cleaning step must be validated for compatibility with MgO, which is sensitive to acidic and alkaline excursions. The post-clean queue time before tunnel barrier deposition is limited; delaying the next layer deposition permits native oxide growth and interface degradation. In practice, the planarization module is placed adjacent to the tunnel barrier deposition tool.

Because the write field strength depends directly on pole tip physical dimension, planarization of electroplated CoNiFe pole layers is treated as a process control step rather than a simple metal clearing operation. Thin-film magnetic write head fabrication on AlTiC wafers integrates the cobalt metal polishing slurry before the write coil insulator and subsequent top pole deposition. The slurry removes CoNiFe overburden while preserving the AlTiC substrate and the hard-baked resist or alumina insulator. The principal difficulty is that cobalt alloys have different electrochemical activity than pure cobalt, so a slurry designed for pure cobalt metal may corrode the nickel-rich phase. The preferred process uses a low-abrasive formulation with high chemical selectivity and low downforce to avoid eroding the underlying alumina. CMP process monitoring includes stylus profilometry according to ISO 4287 and scanning electron microscopy of the pole tip. Edge-fast removal is controlled with a multi-zone head. When selectivity to alumina is insufficient, the top pole gap distance shifts and changes the write field strength. Published data for a specific electronic-grade cobalt slurry on CoNiFe alloys is limited; process qualification on test wafers with patterned pole arrays is required before release.