In copper damascene processing for sub-10 nm logic and 1x nm DRAM devices, the electronic-grade aminopolycarboxylate chelating agent is introduced into hydrogen peroxide–based slurries at 0.15 wt% to 0.60 wt% as-supplied. The compound forms hexadentate coordination complexes with cupric ion Cu²⁺ produced by electrochemical oxidation of Cu(0) at the wafer surface during platen rotation. In this application the removal rate window of 350 nm/min to 650 nm/min on 300 mm patterned wafers is observed only when the chelator-to-copper molar ratio in the point-of-use mixture remains above 1.2:1; below this ratio, copper oxide residues persist as post-polish defects on low-k sidewalls after brush scrubbing. For EDTA-type structures the cupric complex stability constant is log K 18.8 at 25 °C and ionic strength 0.1 M; DTPA-type ligands exceed log K 21.0 under the same conditions. Slurry pH is maintained between 5.2 and 6.8 with a hydrogen peroxide concentration of 0.5 wt% to 2.0 wt% and colloidal silica abrasive at 0.5 wt% to 2.0 wt%. Polishing is performed on a four-zone rotary platform with an IC1000 polyurethane pad, platen speed 70 rpm, head speed 73 rpm, downforce 1.2 psi to 2.0 psi, and slurry flow 150 mL/min to 250 mL/min. Static etch rate measured by blanket wafer immersion in the same slurry formulation is held below 5 nm/min; formulations exceeding 8 nm/min static etch produce copper line dishing above 50 nm at 50 µm linewidth and are rejected for production. The predominant failure mode on manufacturing lines is not removal rate loss but post-platen pad loading from copper-chelate precipitation when the slurry pH drifts above 7.0, which reduces pad conditioning efficiency and increases within-wafer non-uniformity to more than 5% after 450 wafer passes. Incoming rinse water must meet ASTM D5127 Type E-1.2 total oxidizable carbon limits because trace organic contaminants compete with the chelator for Cu²⁺ coordination sites and alter the effective complexation capacity.

What Governs Tungsten Plug Recession Control in Acidic CMP Slurries?

Tungsten contact and via plug CMP in 300 mm DRAM and 3D NAND fabrication is performed with low-pH ferric-based slurries in which the chelating additive functions as a hexadentate ligand for dissolved tungsten species, preventing re-adsorption of tungstic acid onto the oxide stop layer. The formulation uses a chelator concentration of 0.05 wt% to 0.25 wt%, ferric nitrate at 0.1 wt% to 0.5 wt%, and alumina or silica abrasive at 2.0 wt% to 5.0 wt%, with pH adjusted to 2.2 to 3.0 using nitric acid. Tungsten removal rates of 150 nm/min to 350 nm/min and tungsten-to-oxide selectivity above 15:1 are typical for device production, but selectivity falls below 8:1 when the chelator level exceeds 0.4 wt% because the ligand begins to attack the underlying plasma-enhanced tetraethyl orthosilicate oxide in the field region. Within-wafer non-uniformity below 3% is specified for logic contact levels; this limit is reached only after the pad has been conditioned with a diamond disk at 0.6 psi for at least 30 minutes prior to lot start. The most frequently recorded process excursion is tungsten plug recession exceeding 15 nm after the oxide buff step, which correlates with a pH drop below 2.0 and the corresponding increase in tungsten dissolution. In that regime the chelator can no longer buffer the ferric ion hydrolysis equilibrium, and dissolved iron species deposit on the wafer edge as a brownish staining defect. Use of a high-purity electrograde chelator with total metal content below 200 ppb is required because iron and copper contamination above this threshold changes the electrochemical potential of the tungsten surface and increases local galvanic attack at seam interfaces. The wetted parts of the polishing tool are specified in 316L electropolished stainless steel with Ra < 0.4 µm surface finish; passivation is repeated after 500 polishing hours to prevent iron leaching into the acidic slurry. No published family of slurry formulations for this application permits direct substitution of a nitrilotriacetic acid-type chelator without re-qualification of both removal rate and defect density on patterned wafers.

Shallow trench isolation planarization with ceria-based slurries accepts dilute chelator addition only when the silicon nitride-to-oxide selectivity measured on 100 Å thermal oxide remains above 20:1. In this application, the chelating agent is dosed at 0.03 wt% to 0.10 wt% into a slurry containing ceria particles at 0.5 wt% to 1.5 wt% and pH adjusted to 4.0 to 5.5 with a carboxylic acid buffer. The additive complexes trace aluminum, iron, and copper ions introduced from upstream chemical-mechanical polishing waste, thereby reducing soluble metal re-deposition on the polished oxide surface. Polish conditions on 300 mm wafers are typically platen speed 90 rpm, head speed 87 rpm, downforce 3.0 psi to 4.0 psi, and slurry flow 200 mL/min to 300 mL/min; oxide removal rates under these conditions are 250 nm/min to 450 nm/min. Defect count measured by laser surface inspection after double-sided brush scrubbing is held below 50 counts for particles larger than 0.2 µm. Exceeding the upper chelator limit is associated with nitride loss acceleration; the ligand abstracts silicon from the nitride surface and lowers the stop-layer thickness by more than 5 nm on dense array regions. The process window is therefore defined by the ratio of oxide removal rate to nitride removal rate, which is re-measured after each slurry batch change using patterned monitor wafers with 9-point film thickness measurements. Incoming slurry pH and conductivity are controlled within ±0.1 and ±10 µS/cm, respectively, because variation outside this band alters the dissociation state of the chelator and shifts removal rate by up to 15%.

Barrier/Liner Selectivity Control on Ta/TaN and PECVD Low-k Stacked Films

Barrier and liner removal on Ta/TaN films beneath PECVD low-k dielectric layers requires a chelator package that binds both cuprous and cupric ions without dissolving the Si–O framework of the dielectric at alkaline pH. In this application the electronic-grade chelator is blended at 0.1 wt% to 0.3 wt% into a slurry containing colloidal silica at 5 wt% to 10 wt% and hydrogen peroxide at 0.5 wt% to 1.5 wt%, with pH maintained between 8.5 and 10.0. The chemical function is to complex Cu²⁺ released from the copper line during barrier clearing and to prevent its re-deposition as cupric hydroxide on the exposed low-k surface. Ta removal rate under production conditions is 40 nm/min to 90 nm/min, while Cu removal rate is suppressed to less than 20 nm/min to maintain line height. The most sensitive process parameter is the molar ratio of hydrogen peroxide to chelator; values below 5:1 reduce Ta removal rate by passivating the metal surface, while values above 15:1 increase copper in-die loss and produce line resistance shifts above 3%. Low-k damage is monitored by angle-resolved X-ray photoelectron spectroscopy before and after polishing; the acceptable maximum carbon depletion at the surface is 10 atomic%, beyond which the dielectric constant increases by more than 0.2 and RC delay degrades. In high-volume manufacturing, pad life with this slurry chemistry is limited to 300 to 500 wafers per pad before defectivity from chelator–copper complexes exceeds the 100 counts threshold at 0.16 µm defect size. Post-CMP cleaning in this sequence uses a mildly acidic chelator solution to remove residual Ta species and copper; the brush scrubber is operated at 50 N downforce and 30 rpm to avoid pattern collapse on porous low-k lines with aspect ratio above 3:1.

In advanced packaging lines for copper pillar bump processes, the chelating agent is formulated into high-solids silica slurries at 0.3 wt% to 0.7 wt% and combined with a peroxide activator to achieve copper removal rates between 1.0 µm/min and 3.0 µm/min on 200 mm or 300 mm wafers with electroplated copper thickness of 30 µm to 80 µm. The primary process objective is coplanarity across the wafer: the coefficient of variation of remaining copper thickness after CMP is specified at less than 5%, with die-level dishing below 2.0 µm at 100 µm pillar pitch. The chelator prevents re-deposition of copper onto the barrier seed layer and reduces the occurrence of over-plating defects on the pillar sidewall. Polishing is performed on a rigid platen with a hard polyurethane pad, downforce 4.0 psi to 6.0 psi, platen speed 50 rpm to 80 rpm, and slurry flow 100 mL/min to 150 mL/min. The high copper load in this application is not simply a scaling of front-end Cu CMP; the chelator-to-Cu²⁺ binding capacity is exhausted more rapidly in the grooves of the pad, and the resulting copper-chelate precipitate reduces pad openness by 30% after 100 wafer passes. In some production lines this is managed by in-situ pad conditioning with a 150-µm diamond disk at 0.3 psi downforce and by point-of-use dilution of the chelator concentrate to maintain free ligand concentration. The chelator used in this segment must also exhibit a low tendency to foam under high shear: foam height measured by a 500 mL graduated cylinder should remain below 10 mL after 5 minutes settling. Published production data for advanced packaging formulations of this specific chelator type is limited; qualification of each new slurry lot is conducted by pad staining inspection, electrochemical quartz crystal microbalance evaluation, and a 500-wafer defect monitor test.

If Post-CMP Cleaning Requires Trace Metal Extraction at pH 3.8

Post-CMP cleaning chemistries for sub-10 nm interconnects use electrograde chelators at pH 3.5 to 4.5 to remove residual Cu²⁺, Fe³⁺, and Al³⁺ from low-k sidewalls after brush scrubbing. The cleaning solution is prepared by diluting the chelating agent to 0.01 wt% to 0.05 wt% in ultrapure water meeting ASTM D5127 Type E-1.2 resistivity above 18.0 MΩ·cm. The ligand binds metal ions in solution and prevents them from re-adsorbing on the wafer surface during the drying step. The cleaning sequence is typically a two-step process: first, a dilute organic acid solution removes ceria or silica particles; second, the chelator solution extracts ionic metal contamination. Particle removal efficiency on structures with 100 nm half-pitch lines is maintained above 95% for particles larger than 0.1 µm, as measured by scanning electron microscopy review. The most significant constraint is the surface metal impurity budget: after cleaning, total Cu on a bare silicon monitor wafer must remain below 5 × 10¹⁰ atoms/cm², Fe below 1 × 10¹¹ atoms/cm², and Al below 5 × 10¹⁰ atoms/cm² by vapor phase decomposition inductively coupled plasma mass spectrometry. Exceeding the chelator concentration above 0.1 wt% can leave a carboxylate residue on the wafer surface that increases contact resistance by more than 2% at 22 nm contact diameter. The cleaning bath is filtered through a 0.05 µm membrane to remove particulate contamination and is replaced every 8 hours or 1000 wafer passes, whichever occurs first, to avoid microbial growth in the dilute organic solution. This application tolerates no amine-based additives because their alkaline hydrolysis products compete with the chelator for metal coordination and reduce cleaning efficiency.

Sapphire wafer polishing for LED and RF substrate production employs a colloidal silica slurry containing a small amount of chelating agent to complex aluminum ions released from α-Al₂O₃ surfaces under high downforce. In a typical 100 mm c-plane sapphire line, the slurry contains 10 wt% to 20 wt% colloidal silica, 0.1 wt% to 0.4 wt% chelator, and pH 10.0 to 11.0 adjusted with potassium hydroxide. The chelator suppresses the formation of aluminum hydroxide gels on the pad and reduces scratch defects on the polished surface. Material removal rates are between 0.5 µm/h and 1.5 µm/h with a platen speed of 40 rpm and a downforce of 250 g/cm² to 400 g/cm². The main operational incompatibility is with calcium-containing polishing pads or conditioning slurry; calcium ions above 500 ppb form insoluble chelate complexes that deposit on the wafer edge and require additional hydrofluoric acid–based cleaning. Substituting a non-electronic-grade chelator is not permitted because iron contamination above 100 ppb lowers the optical transmittance of the polished sapphire at 450 nm by more than 0.5%. Published data for this specific configuration is limited, and batch-to-batch variation in the chelator’s sodium content is the main factor controlling wafer surface roughness after polishing.