| HS Code | 211640 |
| Product | Acidic Silica Polishing Slurry Electronic/EL Grade |
| Appearance | Milky white translucent liquid |
| Silica Content | 30-40 wt% |
| Ph | 2.0-4.0 |
| Average Particle Size | 50-70 nm |
| Specific Gravity | 1.10-1.20 at 25°C |
| Viscosity | 5-15 cP at 25°C |
| Metal Impurities | <1 ppm each for Na, Fe, Cu, Zn |
| Particle Morphology | Spherical, monodisperse colloidal silica |
| Stability | Resistant to agglomeration under acidic conditions |
| Storage Temperature | 5-35°C |
| Shelf Life | 6 months from date of manufacture |
| Applications | Semiconductor wafer polishing, dielectric CMP, silicon substrate finishing |
As an accredited Acidic Silica Polishing Slurry Electronic/EL Grade factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.
| Packing | Packaged in 4×1-gallon HDPE jugs or 5-gallon pails; acid-resistant, sealed, and labeled for Electronic/EL grade use. |
| Container Loading (20′ FCL) | 20′ FCL: load stabilized acid slurry in sealed drums/pails, secure with bracing, prevent leaks, label electronic grade. |
| Shipping | Ship as hazardous acidic slurry in sealed, corrosion-resistant containers. Ensure UN-compliant labeling for acidity, segregate from metals and bases. Maintain temperature stability to prevent settling or gelation. Electronic/EL grade demands contamination-free packaging, with inert liners and moisture barriers. Include proper documentation, SDS, and spill response measures per transport regulations. |
| Storage | Store in tightly sealed original containers in a clean, cool, dry area away from direct sunlight and incompatible materials. Maintain temperatures between 5–30°C; do not freeze. Avoid contamination from dust, metals, or alkaline substances. Keep containers upright, clearly labeled, and use within shelf life. Gently agitate before use if settling occurs. |
| Shelf Life | Shelf life typically 6-12 months if unopened, stored at recommended temperatures, and protected from freezing or contamination. |
In via and contact plug formation at the 14 nm and 10 nm logic nodes, the tungsten CMP step must remove a chemical-vapor-deposited tungsten overburden from an underlying oxide or nitride stop layer without creating plug recess greater than 5% of via depth. The acidic silica polishing slurry is supplied as a 30–40 wt% SiO₂ concentrate and diluted at point of use to 5–10 wt% SiO₂, with hydrogen peroxide added at 2–4 wt% and ferric nitrate accelerator at 0.01–0.05 wt%; nitric acid adjusts the diluted formulation to pH 2.2–3.5. The blending loop is operated under ISO 14644-1:2015 Class 3 conditions, particle size distribution is verified by dynamic light scattering according to ISO 22412:2017, pH is checked by ASTM E70-19, and trace sodium, potassium, iron, and calcium are maintained below 10 ppb by ICP-OES per ISO 11885:2007 to prevent transistor threshold voltage drift. Polishing is performed on a four-head rotary CMP tool with a 600 mm polyurethane pad, downforce of 2.0–4.5 psi (13.8–31.0 kPa), platen speed of 60–110 rpm, and slurry flow of 100–250 mL/min. Endpoint is triggered by optical emission from the exposed dielectric or by motor-current change; the over-polish window is held to 10–30% after endpoint. Production-line data show that pH drift above 4.0 depresses tungsten removal below 150 nm/min and increases plug protrusions, while pH below 2.0 initiates Ti/TiN liner attack. Finished devices include processors, NAND flash, and DRAM with tungsten contact plugs and vias.
The barrier step that follows bulk copper clearing in dual-damascene interconnects removes Ta/TaN liner and copper residue while preserving the underlying low-k dielectric. The slurry is adjusted to an acidic silica dispersion of 2–8 wt% SiO₂, pH 3.0–4.5, with 0.5–2.0 wt% hydrogen peroxide and 0.05–0.30 wt% benzotriazole or 1,2,4-triazole as a copper passivation agent. The formulation is declared under IEC 62474:2018 material composition schema, and the finished integrated circuit must comply with RoHS Directive 2011/65/EU Annex II restrictions and REACH Regulation (EC) No 1907/2006 Article 33 SVHC disclosure obligations. Barrier CMP is performed on a three-platen platform with low downforce of 1.0–2.5 psi (6.9–17.2 kPa), platen speed of 60–90 rpm, and slurry flow of 150–300 mL/min. Endpoint is determined by friction coefficient change from Ta/TaN to low-k film; the process window targets Ta/TaN removal at 40–80 nm/min, copper removal below 10 nm/min, and low-k loss below 5 nm. On three-platen production tools, pad conditioning frequency below 1 sweep/min produces low-k surface scratching from agglomerated silica particles. The terminal products are system-on-chip, graphics processor, AI accelerator, and application processor integrated circuits with copper/low-k interconnects at 7 nm, 5 nm, and 3 nm nodes.
The polishing station for 150 mm and 200 mm silicon carbide wafers following diamond lapping deploys an acidic silica slurry to remove subsurface damage and reduce surface roughness to epi-ready levels. The supplied concentrate contains 15–30 wt% colloidal silica, diluted 1:1 to 1:3 with deionized water and supplemented with 0.5–2.0 wt% hydrogen peroxide; pH is held at 2.5–4.0. Particle size is maintained at 30–70 nm by ISO 22412:2017, pH is verified by ASTM E70-19, and surface roughness after polishing is measured according to ISO 4287:1997 with an interferometer of 0.1 nm vertical resolution. CMP is conducted on a single-side polisher with a cast-iron platen and closed-cell polyurethane pad under 4.0–6.0 psi downforce, 40–80 rpm platen speed, and 150–300 mL/min slurry flow. The removal rate on the silicon face is 30–100 nm/hr, so a 1.0–2.0 µm damage layer requires 6–12 hrs of processing. Batch-to-batch zeta potential reduction below 15 mV causes particle deposition in pad grooves and raises micro-scratch counts from 10 to 80 per 150 mm wafer. Terminal products are epi-ready SiC substrates for 600 V to 3.3 kV MOSFETs and Schottky barrier diodes used in electric vehicle inverters, photovoltaic inverters, industrial motor drives, and 5G base station power amplifiers. Iron contamination above 10¹¹ atoms/cm² degrades carrier lifetime and requires post-CMP chelating cleanup.
For GaAs pHEMT and InP HBT backside thinning, the transition from mechanical grinding to wet chemical etch requires a non-alkaline polishing medium because alkaline solutions increase gallium and arsenic leaching rates and roughen sidewall edges. The slurry is diluted to 2–8 wt% SiO₂, pH 2.0–4.0, with 0.5–1.5 wt% hydrogen peroxide and 0.01–0.1 wt% citric acid as a chelator. Cleanroom handling follows ISO 14644-1:2015 Class 3, and material declarations are issued under IEC 62474:2018. Backside thinning is performed on a wafer mounter with UV-curable adhesive on a sapphire carrier, followed by a CMP tool with stainless steel platen and polyurethane pad at 1.0–2.5 psi downforce, 60–100 rpm platen speed, and 80–200 mL/min slurry flow. Material removal rate for GaAs is 300–800 nm/min; for InP it is 150–500 nm/min. Final thickness is controlled by infrared interferometry to ±1 µm. Edge chipping beneath the sapphire carrier appears when downforce exceeds 2.5 psi and carrier flatness tolerance exceeds 5 µm. Waste streams must be segregated from strongly reducing solutions to avoid arsine generation. Terminal components include RF power amplifiers, low-noise amplifiers, terahertz diodes, VCSELs, edge-emitting lasers, and photodetectors for optical transceivers, smartphone RF front-ends, and LiDAR modules.
Because 300 mm reclaimed wafers retain residual device structures, damaged dielectric plugs, and metal contamination after stripping and wet cleaning, the CMP step must remove 1.0–5.0 µm of surface silicon without introducing edge roll-off or thickness non-uniformity. The acidic silica slurry is mixed at point of use to 1–5 wt% SiO₂, pH 2.5–3.5, with no oxidizer for bare silicon reclaim or with 0.1–0.5 wt% hydrogen peroxide when tungsten or copper residue requires selective removal. Surface roughness is measured according to ISO 4287:1997, slurry particle size according to ISO 22412:2017, and slurry pH according to ASTM E70-19. Single-side or double-side polishing is performed on a four-head polisher at 2.0–4.0 psi downforce, 50–90 rpm platen speed, and 150–300 mL/min slurry flow. Silicon removal rate in acidic silica is 200–600 nm/min; process time is calculated from a pre-polish thickness map to maintain final total thickness variation below 2.0 µm. Monitor wafer history shows that final TTV below 2.0 µm is achieved only when the pre-polish thickness map is updated at 1.0 µm resolution. If slurry pH drops below 2.0, pad wear rate increases and polyurethane pad debris raises defect counts. Terminal products include reclaimed test wafers, reconditioned monitor wafers, SOI wafers for MEMS, RF switches, and silicon photonics.
Through-silicon via copper overburden removal for 2.5D and 3D packaging uses a high-removal-rate acidic silica slurry to reduce thick electroplated copper films of 5–30 µm to the barrier level on the wafer backside or frontside. The concentrate is diluted to 10–20 wt% SiO₂, pH 3.0–4.0, with 1.0–3.0 wt% hydrogen peroxide and 0.05–0.2 wt% corrosion inhibitor; phosphoric acid serves as the pH adjuster. Slurry handling is validated under ISO 14644-1:2015 Class 4 conditions, particle size distribution is monitored by ISO 22412:2017, and pH is checked by ASTM E70-19. CMP is performed on a large-platen packaging polisher with 1.5–3.5 psi downforce, 70–120 rpm platen speed, and 200–400 mL/min slurry flow. Endpoint uses an eddy current thickness sensor with feedback to reduce downforce during barrier clearing. Copper removal rate is 0.8–1.8 µm/min with within-wafer non-uniformity below 5%. High-removal-rate copper CMP produces pad debris that requires conditioning every 2 min to maintain within-wafer uniformity. Terminal products include high-bandwidth memory stacks, 2.5D interposers, 3D SoC stacking, and high-density fan-out packages for data center and AI accelerator modules.
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Acidic silica polishing slurry designated for electronic/EL grade applications is a colloidal dispersion of amorphous silica nanoparticles in an acidic aqueous matrix. The material is specified for chemical mechanical planarization and precision surface finishing where trace metal contamination, large-particle counts, and organic residue must remain below semiconductor process limits. Typical release values include silica concentration 20–40 wt%, dynamic light scattering median particle diameter D50 of 30–80 nm per ISO 22412:2017, pH 2.0–3.5 by glass electrode per ASTM E70-19, and dynamic viscosity 1.5–5.0 mPa·s at 25 °C per ASTM D2196-20. Electronic/EL grade is distinguished by cation impurity limits typically below 100 ppb sodium, 100 ppb potassium, 50 ppb iron, 25 ppb copper, 50 ppb aluminum, and 25 ppb chromium, as determined by inductively coupled plasma mass spectrometry in accordance with ASTM D5673-16. The acidic pH range is selected to control metal surface chemistry during polishing. Model identification is supplier-specific and generally encodes nominal silica content and particle size class; because no unified industry nomenclature exists, procurement documents should reference lot release values rather than a proprietary model number alone. The slurry is free of intentionally added oxidizers in the base formulation; if an oxidizer is required for barrier metal removal, it is mixed at the point of use.
The primary difference is the acidic pH regime. Alkaline colloidal silica slurries typically operate at pH 10–11 to maintain negative zeta potential and particle repulsion; acidic electronic/EL grade material operates at pH 2.0–3.5, close to the silica isoelectric point at pH 2.0–2.5. This creates a narrower stability window and requires charge stabilizers or high-purity acidulants. The EL grade also imposes lower metal contamination than general polishing grades. General optical polishing slurries may release sodium above 1 ppm; electronic/EL grade material is specified below 100 ppb for sodium and below 50 ppb for iron. Large-particle counts are controlled by point-of-packaging filtration, with particles sized ≥0.5 µm limited to fewer than 100 counts/mL in many purchase specifications. Total organic carbon is controlled to <50 ppm to reduce organic residues on metal lines and dielectric interfaces. Particle size distribution width is also narrower: the span (D90−D10)/D50 is controlled below 1.0 for electronic/EL grade material, while general grades may exceed 1.5. The narrow distribution reduces scratch defects and improves within-wafer non-uniformity.
| Parameter | Acidic Silica EL Grade | Alkaline Colloidal Silica | General Polishing Grade |
|---|---|---|---|
| pH range | 2.0–3.5 | 10–11 | 7–11 |
| Silica concentration | 20–40 wt% | 20–40 wt% | 15–30 wt% |
| Median particle diameter D50 | 30–80 nm | 20–100 nm | 50–150 nm |
| Sodium impurity | <100 ppb | <1 ppm | >1 ppm |
| Iron impurity | <50 ppb | <200 ppb | >500 ppb |
| Large-particle count ≥0.5 µm | <100 counts/mL | <500 counts/mL | >1,000 counts/mL |
Lower-purity grades are not acceptable for electronic/EL applications because mobile alkali ions can migrate into gate oxide and shift threshold voltage. Sodium and potassium are particularly critical due to high mobility in silicon dioxide at temperatures above 150 °C; general polishing grades may exceed 1 ppm sodium, while electronic/EL grade is controlled below 100 ppb. A single contaminated slurry batch with sodium above 500 ppb can shift flatband voltage by several tens of millivolts on 200 mm test wafers. Published data for this specific configuration is limited, but the restriction is a standard contamination control requirement in semiconductor process integration.
The electronic/EL grade slurry is released against a certificate of analysis covering particle size distribution, solids content, pH, viscosity, specific gravity, cation impurities, anion impurities, large-particle counts, and total organic carbon. Incoming inspection at wafer fabs commonly repeats pH, viscosity, particle size, and large-particle counts before connecting the slurry to the distribution loop. The following table lists typical release ranges and corresponding test methods. Values are supplier-specific and should be confirmed against the applicable certificate of analysis.
| Property | Method / Equipment | Typical Release Range |
|---|---|---|
| pH | ASTM E70-19, glass electrode | 2.0–3.5 |
| Dynamic viscosity at 25 °C | ASTM D2196-20, rotational viscometer | 1.5–5.0 mPa·s |
| Median particle diameter D50 | ISO 22412:2017, dynamic light scattering | 30–80 nm |
| Silica content | Gravimetric loss on drying per ISO 787-2:2021 | 20–40 wt% |
| Sodium | ASTM D5673-16, ICP-MS | <100 ppb |
| Iron | ASTM D5673-16, ICP-MS | <50 ppb |
| Copper | ASTM D5673-16, ICP-MS | <25 ppb |
| Large-particle count ≥0.5 µm | Light-scattering particle counter, ISO 21501-1:2009 | <100 counts/mL |
| Total organic carbon | Wet oxidation / NDIR per ASTM D7573-18 | <50 ppm |
Anion impurities such as chloride, nitrate, and sulfate are controlled below 10 ppm by ion chromatography per ASTM D4327-17 to avoid corrosion of copper and tantalum barrier layers. The limit of quantitation for sodium and potassium by direct injection ICP-MS is typically 1 ppb. Incoming inspection often includes a 48-hour static settlement test at 25 °C; settled volume above 1 vol% indicates instability. The product is assigned a shelf life of 12 months in unopened containers when stored at 5–35 °C.
In oxide chemical mechanical planarization on 200 mm and 300 mm wafer platforms, the slurry is dispensed onto a polyurethane or poromeric pad through a peristaltic or bellows pump at 50–200 mL/min. Rotary CMP tools with independent platen and carrier speed control are run at platen speed 30–90 rpm, carrier speed 28–90 rpm, and downforce 2–6 psi. Removal rate of plasma-enhanced chemical vapor deposition silicon dioxide is characterized by high-resolution profilometry using a 4 µm thermal oxide step-height standard traceable to ISO 5436-1:2000; within-wafer non-uniformity is calculated from a 49-point diameter scan with 3 mm edge exclusion. For an acidic silica slurry at 30 wt% solids, oxide removal rates of 150–350 nm/min have been reported at 4 psi downforce and 90 rpm platen speed; however, published data for this specific configuration is limited and pad conditioning, slurry flow, and wafer pattern density shift the value. The slurry is also used after backside grinding of silicon wafers to remove subsurface damage; in that application it is typically diluted with ultrapure water to 10–20 wt% solids and delivered through a 0.5 µm point-of-use filter.
Pad conditioning is performed with a diamond disk at 100–200 rpm platen speed and 5–10 lbf downforce; pad surface temperature is maintained below 45 °C. Endpoint detection is performed by motor current or optical reflectometry. Slurry flow interruption should be avoided because dried silica forms crystalline deposits on pad grooves and carrier surfaces; if flow stops for more than 2 min, the line must be purged with ultrapure water.
The replacement decision is not a direct substitution. Acidic silica at pH 2.0–3.5 exhibits lower chemical dissolution of silicon dioxide than alkaline formulations; removal is dominated by mechanical abrasion and pad-particle interaction. At 4 psi downforce, the removal rate may be 20–35% lower than an alkaline slurry with the same abrasive content. The acidic environment suppresses oxide dissolution but increases the risk of pad hardness drift and slurry drying. Slurry pH must be monitored after dilution with ultrapure water because carbon dioxide absorption can shift pH by 0.2–0.5 units within 24 h in open supply vessels; closed pressurized canister systems with 0.05 µm membrane filters and nitrogen blanketing are used to prevent pH drift and biological growth. The zeta potential of silica particles is near zero at pH 2.0–2.5; at pH 2.8–3.5 the particles carry sufficient negative charge for electrostatic repulsion. Formulated batches are therefore held at the upper end of the acidic range to maintain dispersion while avoiding alkaline metal dissolution. Addition of amine-based additives or cationic surfactants must be avoided because particle bridging and gelation can occur in less than 6 h at 25 °C. For shallow trench isolation polishing, oxide-to-nitride selectivity below 4:1 is expected only with ceria or surfactant-modified abrasives; published data for this specific configuration is limited.
Colloidal stability is a primary shelf-life limitation. The acidic slurry is supplied at 20–40 wt% silica and pH 2.0–3.5. Because the silica isoelectric point is pH 2.0–2.5, settled solids can form a hard cake. Redispersion is possible only with low-shear paddle agitation at 10–30 rpm using PTFE-coated impellers; high-shear rotor-stator mixing above 1,000 rpm can produce irreversible agglomeration and viscosity increase. The product is filtered at point of packaging through 0.5 µm polypropylene depth filters followed by 0.1 µm polyethersulfone membrane filters. Post-filtration large-particle counts are verified by light-scattering particle counters calibrated per ISO 21501-1:2009; counts above 100 particles/mL at ≥0.5 µm are cause for rejection. Storage temperature is maintained at 5–35 °C; exposure above 40 °C accelerates silica dissolution and oligomerization, shifting D50 upward by 5–15 nm over 30 days. Freeze–thaw cycling is prohibited because ice-crystal-induced particle compression leads to gelation. At 25 °C, dynamic viscosity remains 1.5–5.0 mPa·s per ASTM D2196-20; a drift above 0.5 mPa·s indicates aggregation. Storage tanks and transfer lines are specified in high-density polyethylene or fluoropolymer-lined stainless steel to limit iron release below 10 ppb.
In a semiconductor fab distribution loop, the slurry is recirculated at 0.5–2 m/s through 1/2-inch high-density polyethylene tubing. Flow below 0.3 m/s permits particle settling in horizontal runs; flow above 2 m/s causes shear-induced aggregation. The loop is filtered continuously through 0.1 µm polyethersulfone filters with a pressure drop below 0.5 bar; a differential pressure above 1.0 bar indicates filter loading and requires replacement before large-particle counts rise. Return-line pressure is controlled to 0.2–0.5 bar to avoid cavitation at the pump head.
On a copper barrier polishing line, the acidic silica slurry is used after bulk copper removal to clear residual tantalum/tantalum nitride barrier and dielectric oxide. The slurry is dispensed at 100–200 mL/min onto a poromeric pad conditioned in situ with a diamond disk; platen speed is held at 60–90 rpm, and carrier backpressure is controlled to 2–4 psi. The low pH assists in removing cuprous oxide residues but necessitates immediate post-CMP cleaning with dilute organic acid or buffered fluoride solutions to prevent copper corrosion. The process window for pH is narrower than for oxide-only polishing: a drift of 0.3 pH units increases copper dissolution and creates metal line recess. The slurry is incompatible with strong oxidizers such as 30% hydrogen peroxide in the same delivery line because exothermic decomposition and silica gelation can occur; segregation of slurry and oxidizer lines is required.
