In AI server copper-clad laminates operating at 112 Gbps and 224 Gbps PAM4, the core layer resin matrix is formulated with a low-polarity hydrocarbon resin blended into polyphenylene ether or modified polyphenylene ether. The addition level in varnish solids commonly falls between 15 wt% and 35 wt%, depending on glass style, filler loading, and target dielectric constant. Material acceptance is benchmarked against IPC-4101E/126 and IPC-4101E/130 slash sheet requirements. Dielectric constant at 10 GHz is measured by IPC-TM-650 2.5.5.13 and is controlled between 3.0 and 3.4. Dissipation factor at 10 GHz is held between 0.0015 and 0.0025. The hydrocarbon resin functions as a crosslinkable low-viscosity component, enabling higher silica filler loading without destroying varnish shelf life or prepreg flexibility. Spherical silica filler is incorporated at 20 wt% to 60 wt% of total solids. When ambient relative humidity exceeds 60%, the filler is pre-dried at 150 °C for 4 h; failure to do so permits silane coupling agents to hydrolyze and raises cured laminate dissipation factor. Varnish is prepared in jacketed high-shear dispersers using methyl ethyl ketone and toluene. The coated glass is processed through a horizontal treater with zone temperatures from 80 °C to 170 °C. Residual solvent after treating is maintained below 0.5 wt%. The prepreg is laminated against low-profile copper foil with surface roughness Rz below 2.0 µm. Copper foil roughness above this threshold increases conductor loss and obscures the dielectric improvement supplied by the hydrocarbon resin. The lamination cycle is held at 200 °C to 220 °C under 2.5 MPa to 4.0 MPa for 90 min to 120 min. The resulting laminate is converted into 800G and 1.6T switch line cards, router boards, and high-speed backplane panels.

What Changes in Prepreg Rheology Arise When Hydrocarbon Resin Replaces a Portion of Epoxy in Multipanel Lamination?

When ultra-low-loss hydrocarbon resin replaces 20 phr to 40 phr of epoxy solids in a prepreg varnish, the minimum melt viscosity at lamination temperature drops relative to an unmodified epoxy formulation. Parallel-plate rheometry under a 5 °C/min ramp, evaluated in accordance with ASTM D4440-15, records a minimum dynamic viscosity between 1,000 Pa·s and 10,000 Pa·s at 150 °C to 180 °C. The exact minimum depends on filler content, resin molecular weight, and the degree of B-stage advancement. The reduction in melt viscosity improves fill around patterned copper features and buried via holes, but addition above 40 phr reduces B-stage tack and can produce dry glass-bundle edges during horizontal treating. In production, the prepreg is coated onto low-Dk E-glass or quartz glass with a reverse roll coater. The treater line speed is limited by gel time rather than drying capacity. Gel time at 171 °C is controlled between 150 s and 250 s by IPC-TM-650 2.3.18. Volatile content after treating is held below 0.5 wt% by IPC-TM-650 2.3.19. Resin flow is tested to IPC-TM-650 2.3.17 and is typically set between 2% and 8% depending on lamination pressure and copper thickness. The formulation is incompatible with strong amine-based epoxy catalysts when the hydrocarbon resin contains pendant unsaturation. Such catalysts can initiate premature exothermic crosslinking inside the treater and drop gel time below 120 s. The lamination press uses vacuum-assisted heating at 200 °C to 210 °C with 2.5 MPa to 3.5 MPa applied in staged steps to avoid resin starvation. Cool-down under pressure is required when dielectric spacing between adjacent signal layers falls below 100 µm. Direct comparative data for every hydrocarbon-to-epoxy ratio are limited in public literature; the ranges above align with production-scale prepreg line audits and CCL vendor data sheets. The resulting multilayer panels are processed into 24-layer to 36-layer AI server boards with backdrilled high-speed signal vias and buried capacitance layers.

A Different Stress Field Governs OAM 2.0 Accelerator Module Baseboards

OAM 2.0 accelerator module baseboards do not tolerate the same resin-rich formulations used in thin switch line cards. The stack-up often exceeds 24 layers with board thickness above 3.0 mm. The resin matrix must balance low dielectric loss against high modulus and low coefficient of thermal expansion. Hydrocarbon resin loading is therefore kept at the lower end of the process window, typically 10 wt% to 20 wt% of varnish solids. Higher loadings reduce lamination viscosity but raise Z-axis CTE beyond acceptable limits. Z-axis CTE below glass transition is measured by IPC-TM-650 2.4.24.5 and is controlled below 45 ppm/K. Warpage after simulated reflow is measured by IPC-TM-650 2.4.22 and is kept below 0.75% on panel sizes above 500 mm × 600 mm. The baseboard is pressed in multiple lamination cycles. Inner-layer cores are first laminated and etched, then outer-layer prepregs and copper foil are added in a second press cycle. After each cycle, panels are cooled under 0.5 MPa to 1.0 MPa to reduce residual stress. The low hydrocarbon resin loading improves fill around thick copper planes, which can exceed 70 µm in power distribution layers. However, this resin alone does not eliminate the need for silica filler. Filler content is raised to 55 wt% to 70 wt% in outer prepregs to control CTE and drillability. Mechanical drilling of the thick stack-up uses 0.25 mm to 0.35 mm bits with retraction feed rates below 2.0 m/min to avoid smear. Desmear and via cleaning are carried out in alkaline permanganate at 80 °C for 10 min to 15 min. The finished baseboards are used for OCP OAM 2.0 accelerator modules with high-layer-count differential pairs and dense power delivery networks.

For chiplet package substrates used in OAM accelerator modules, the ultra-low-loss hydrocarbon resin is incorporated into build-up dielectric films rather than core laminates. The dielectric film is coated onto a 25 µm to 50 µm PET carrier. Coated thickness after drying is 15 µm to 40 µm. The resin is blended with epoxy or maleimide components at 20 wt% to 35 wt% hydrocarbon resin solids to lower dielectric loss without destroying laser via processability. After vacuum lamination onto a core substrate at 100 °C to 130 °C, the film is thermally cured at 180 °C to 220 °C for 60 min to 120 min. Laser via drilling uses a UV/CO2 hybrid system. Laser fluence is kept below the threshold that produces carbonaceous residue along the via sidewall. Desmear is then performed with alkaline permanganate. The cured dielectric must exhibit a dissipation factor below 0.005 at 10 GHz and water absorption below 0.15 wt% after 24 h at 23 °C. Moisture uptake is measured by IPC-TM-650 2.6.2.1. Higher hydrocarbon resin loadings above 35 wt% reduce film elongation and increase the risk of microcracking during thermal cycling. Peel strength of the build-up dielectric to copper after roughening is checked to IPC-TM-650 2.4.8. The end application is a coreless or thin-core chiplet package substrate with 8 µm to 12 µm line/space routing for die-to-die interconnects.

When Co-Packaged Optics Place Dielectric Loss Constraints on Waveguide-Adjacent Substrates

When an OAM module integrates co-packaged optics, the substrate adjacent to the optical engine routes 56 GBd or 112 GBd PAM4 driver signals. The hydrocarbon resin is loaded at 25 wt% to 35 wt% of the dielectric solids to maintain stable dielectric constant and low dissipation factor at higher frequencies. The substrate is often a thin coreless build-up with laser-drilled microvias. Differential impedance is designed for 100 Ω. The dielectric constant used for stack-up calculation is taken from IPC-TM-650 2.5.5.13 data measured at 10 GHz and extrapolated to 50 GHz. Publicly available data for exact high-frequency performance of every hydrocarbon resin in co-packaged optics substrates are limited. When such data are absent, the design uses the 10 GHz Dk and Df values as conservative inputs. The cured dielectric film must withstand 260 °C reflow for 60 s without void formation or delamination. Moisture absorption is kept below 0.15 wt% to prevent impedance drift of 50 Ω single-ended and 100 Ω differential lines. The laminated substrate is laser drilled with 50 µm to 80 µm vias and filled with copper electroplating. The final optical engine substrate is assembled with VCSEL or silicon photonics chips and terminated by 400G or 800G optical transceivers. The process boundary is narrow: residual solvent above 0.3 wt% in the build-up film causes outgassing and microvoid formation during the 260 °C reflow step.