| HS Code | 858786 |
| Material | BT Resin (BMI-Triazine) |
| Application | IC Packaging Substrate |
| Glass Transition Temperature | >200 °C |
| Dielectric Constant Dk At 1 Mhz | 4.0 - 4.5 |
| Dissipation Factor Df At 1 Mhz | 0.008 - 0.015 |
| Moisture Absorption | 0.2 - 0.5% |
| Coefficient Of Thermal Expansion Cte α1 | 10 - 15 ppm/°C |
| Coefficient Of Thermal Expansion Cte α2 | 30 - 50 ppm/°C |
| Thermal Conductivity | 0.2 - 0.4 W/m·K |
| Flexural Strength | 300 - 400 MPa |
| Flexural Modulus | 20 - 30 GPa |
| Copper Peel Strength | 0.8 - 1.2 kN/m |
| Volume Resistivity | >1.0E+14 Ω·cm |
| Surface Resistivity | >1.0E+14 Ω |
| Dielectric Breakdown Strength | >40 kV/mm |
| Flame Retardancy | UL94 V-0 |
| Specific Gravity | 1.8 - 2.0 |
As an accredited BT Resin (BMI-Triazine) High-Temperature (Tg>200°C) for IC Packaging factory, we enforce strict quality protocols—every batch undergoes rigorous testing to ensure consistent efficacy and safety standards.
| Packing | BT Resin (BMI-Triazine) high-temperature (Tg>200°C) for IC packaging; supplied as 1 kg sealed powder in nitrogen-flushed aluminum bag. |
| Container Loading (20′ FCL) | 20′ FCL: BT Resin (Tg>200°C) shipped in drums on pallets, secure, dry, for IC packaging. |
| Shipping | This BT Resin ships in sealed, moisture-barrier containers to protect its high-temperature properties. Store in a cool, dry place below 25°C, away from direct sunlight and humidity. Handle with clean, dry tools to prevent contamination. Standard dry freight shipping is acceptable, avoiding extreme temperatures or impacts. |
| Storage | Store BT Resin (BMI-Triazine) in a sealed, moisture-proof container in a cool, dry environment below 25°C. Protect from direct sunlight, heat, and humidity to prevent premature curing or moisture absorption. Keep original packaging intact until use, and follow manufacturer-recommended shelf life and handling procedures. |
| Shelf Life | Shelf life is typically 6 months from manufacture when stored sealed in a cool, dry environment. |
For high-layer-count flip-chip ball grid array (FC-BGA) substrates used in server central processing units and graphics processors, BT resin is processed as a solvent-borne varnish for woven-glass prepreg. The bismaleimide–triazine network cures through parallel reactions: cyanate ester cyclotrimerization to sym-triazine rings between 170 °C and 220 °C, and maleimide addition across the same temperature window. Commercial varnishes are compounded to 55–65 wt% total solids with 25–40 wt% of total solids as fused silica dispersed in methyl ethyl ketone or cyclopentanone. Prepreg lamination onto low-profile electrodeposited copper foil occurs in vacuum-assisted hot presses at 190–230 °C under 2.5–3.5 MPa for 90–120 min; the resulting core sheets of 0.4–0.8 mm thickness must exhibit DMA Tg above 200 °C when tested according to IPC-TM-650 2.4.24.4 and a residual exotherm below 5 J/g by differential scanning calorimetry. The network’s high aromatic density limits moisture absorption to 0.1–0.3 wt% after 85 °C/85 %RH conditioning; this becomes critical because absorbed moisture vaporizes and can induce blistering at Sn-Ag-Cu reflow peak temperatures of 245–260 °C. For electrochemical reliability, the cured laminate is subjected to conductive anodic filament testing per IPC-TM-650 2.6.14.1 at 85 °C, 85 %RH, 15 V DC, with no conductive filament growth after 1000 h at 0.5 mm hole-to-hole spacing. Build-up dielectric layers surrounding plated through-holes use the same BT chemistry with reduced filler content for laser drillability; UV laser vias at 355 nm with fluence of 0.8–1.5 J/cm² are desmeared in alkaline permanganate before electroless copper deposition. Terminal substrates for FPGA and accelerator packages contain 4–8 build-up layers and pass IPC-6012 Class 3 inspection for annular ring and void criteria.
Table 1. Comparative BT/Glass Laminate Formulation Data for FC-BGA Core and Build-Up Positions
| Position | Resin content (wt%) | SiO₂ filler (wt%) | DMA Tg (°C) | CTE x/y (ppm/°C) | Dk at 10 GHz | Df at 10 GHz |
|---|---|---|---|---|---|---|
| Core laminate | 60–65 | 30–40 | 215–230 | 12–14 | 3.8–4.2 | 0.007–0.009 |
| Build-up dielectric | 70–80 | 10–20 | 205–220 | 18–22 | 3.4–3.8 | 0.005–0.007 |
| Low-loss RF build-up | 75–85 | 5–15 | 205–215 | 20–25 | 3.2–3.6 | 0.003–0.006 |
Dk and Df are measured per IPC-TM-650 2.5.5.9; values represent typical supplier ranges. Published data for exact halogen-free low-loss BT/triazine formulations are formulation-specific and not fully disclosed in public technical bulletins.
Memory substrate strip lamination presents a warpage threshold that BT resin chemistry addresses through a high modulus plateau above 200 °C. For LPDDR5 and DDR5 package substrate strips, the laminate consists of glass fabric style 1078 or 2116 impregnated with BT varnish, then pressed at 190–230 °C and 2.5–4.0 MPa. Strip format of 240 mm × 65 mm with dielectric thickness 0.12–0.22 mm is standard. The critical variable is z-axis expansion: the glass-rich core constrains in-plane expansion to 12–15 ppm/°C, while z-axis expansion between 50 °C and 260 °C is controlled to 2.5–3.0 % through silica content of 10–20 wt% in build-up resin. Warpage after reflow is measured by shadow moiré per JEDEC JESD22-B112; strip-level coplanarity must remain below 0.20 mm edge-to-edge after three 260 °C reflow cycles. Substrate suppliers use BT with a storage modulus of 1.5–3.0 GPa at 250 °C by DMA to resist creep during copper anneal. The plating process pairs 12 µm electrodeposited copper foil with blind microvia aspect ratios of 0.7:1–1.0:1, and resin smear from mechanical drilling is cleared with permanganate desmear before electroless copper. Terminal packages are fine-pitch ball grid arrays with 0.40–0.65 mm ball pitch and 100–400 balls per package; these are qualified to IPC-6013 and JEDEC JESD22-A113 through MSL 3 preconditioning. Halogen-free formulations meet IEC 61249-2-21 and remain compatible with electroless nickel immersion gold surface finishes at 0.03–0.05 µm gold thickness.
Antenna-in-package and RF front-end SiP modules operating in the 24.25–29.50 GHz band require substrate loss tangents below 0.006 to limit insertion loss. BT resin grades with reduced polar triazine content and styrene-ethylene-butylene-modified bismaleimide segments are laminated into low-loss interposers. Dielectric constant is 3.2–3.6 and dissipation factor is 0.003–0.006 at 10 GHz when tested by IPC-TM-650 2.5.5.9; at 28 GHz, published multi-vendor data remain limited, although the ranking among commercial grades is generally retained. Low-profile copper foil with Rz 1.5–2.0 µm and matte-side silane treatment is specified because conductor roughness increases insertion loss with frequency. Laser via formation uses 355 nm UV at 6–12 µJ pulse energy and 50–100 kHz repetition rate; post-drill desmear with 50–70 g/L KMnO₄ in 1.0–1.5 mol/L NaOH at 60–70 °C removes 0.2–0.5 µm of residue. Plated through-hole and blind via walls are then copper electroplated to 15–20 µm thickness. The finished interposer has 50 µm line/space and 0.15 mm solder mask dams. Compliance for flip-chip land patterns and solder mask registration follows IPC-6012, and halogen-free flame retardancy satisfies UL 94 V-0 at 0.20 mm thickness. A network containing 70–80 wt% resin solids in the build-up layer provides laser ablation rates of 0.3–0.6 µm/pulse; higher filler loadings above 20 wt% reduce ablation rate and increase via-wall taper beyond 70°, so RF build-up grades keep spherical silica below 15 wt%.
Precut BT/glass laminate strip for wire-bonded chip-scale packages is supplied at 0.10 mm thickness with 50 µm/50 µm line/space after subtractive etching. Substrate singulation by saw or laser occurs at 40–50 °C to avoid resin chipping; the terminal package is a 5 mm × 5 mm chip-scale package with 0.50 mm pitch and 2–4 rows of wire bond pads.
Automotive engine-control and transmission IC packages use BT substrates because the triazine rings retard thermo-oxidative degradation at 175 °C for 1000 h under AEC-Q100 high-temperature storage life conditions. The failure mode most often observed is not bulk Tg loss, but copper-to-resin adhesion degradation; initial peel strength of 0.8–1.2 N/mm per IPC-TM-650 2.4.8 drops below 0.4 N/mm after 1000 h if the copper foil chromium-zinc oxide conversion coating is insufficient or if residual chloride from plating exceeds 10 ppm ion contamination. BT laminates for this segment are therefore supplied with 15–20 wt% cycloaliphatic epoxy flexibilizer blended into the varnish to reduce core sheet microcracking during thermal cycling from -55 °C to 150 °C per JEDEC JESD22-A104. The cured glass-transition temperature must still exceed 200 °C; the flexibilizer lowers Tg by 10–15 °C, so process compensation through post-cure at 220 °C for 4 h is required. Moisture sensitivity is a second boundary: after 85 °C/85 %RH exposure for 168 h, the substrate must pass three 260 °C reflow cycles without blistering, corresponding to JEDEC JESD22-A113 MSL 3. Solder mask for these packages is a high-Tg phenolic-cured epoxy selected for 150 °C continuous operating temperature; adhesion after thermal aging is tested by cross-hatch tape per ASTM D3359, with no edge lift. Through-hole vias in 0.20 mm pitch require plating elongation above 8 % to tolerate z-axis expansion, which reaches 2.5–3.0 % from 50 °C to 260 °C. Terminal packages are 48-pin to 176-pin BGA formats, qualified under AEC-Q100 Grade 1, and mounted on engine surfaces where continuous ambient temperatures approach 125 °C with transient excursions to 150 °C.
Coreless substrate processing for application processors selects BT-based build-up film on a temporary carrier; the carrier is separated after redistribution-layer lamination, eliminating the rigid core and lowering loop inductance. Build-up films are slot-die coated at 20–35 µm dry thickness from BT resin solutions containing 5–10 wt% nano-silica. Sequential lamination at 170–210 °C for 30–60 min per layer uses a vacuum press at 0.5–1.5 MPa, lower than core lamination to avoid carrier warpage. After laser via formation at 355 nm, via diameters are 40–60 µm, and desmear-to-copper thickness loss is kept below 0.3 µm. The absence of a core shifts in-plane stiffness to the copper redistribution layers, so the BT film must provide a Young’s modulus of 3–4 GPa after cure and elongation of 5–8 %. Final package size is typically 10 mm × 10 mm to 15 mm × 15 mm for mobile application processors with 0.35 mm bump pitch. Compliance data for coreless substrates commonly cite IPC-6013 for microvia void criteria and JEDEC JESD22-A104 for -55 °C to 125 °C cycling.
Double-side fine-line BT substrates derive peel strength less from the BT matrix than from foil surface treatment. Standard low-profile foils with Rz 1.5–2.0 µm and chromium-zinc oxide conversion coatings yield initial peel strengths of 0.7–1.0 N/mm; very low-profile foils below 1.0 µm Rz can reduce peel strength to 0.3–0.5 N/mm, which is below the 0.4 N/mm internal acceptance criterion for rigid-to-build-up film interfaces. For 0.06–0.10 mm thin laminates, the trade-off between signal integrity and peel strength is managed by reducing conductor roughness only on high-frequency layers while retaining 2–3 µm Rz on power and ground planes. Substrate suppliers subject BT build-up films to IPC-TM-650 2.4.8 peel testing after thermal stress at 150 °C for 1000 h and after 85 °C/85 %RH for 168 h. A BT resin with 70–80 wt% solids and 10–15 wt% spherical silica has a cured fracture toughness of 0.8–1.2 MPa·m1/2; cohesive failure within the resin rather than interfacial failure at the foil indicates sufficient silane coupling. Solder resist adhesion on BT build-up films also requires the same copper surface treatment, with a minimum solder dam width of 0.10 mm and mask lift-off below 5 % after 260 °C reflow. Terminal applications include double-data-rate memory modules and compact system-in-package substrates where two-metal-layer BT films are processed into 25 µm line/space patterns.
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BT resin (BMI-Triazine) high-temperature (Tg>200 °C) for IC packaging is a thermosetting copolymer network formed by the co-reaction of bismaleimide and cyanate ester/triazine precursors. It is used mainly as a rigid core laminate or prepreg in ball-grid-array substrates, chip-scale packages, flip-chip chip carriers, and system-in-package interposers. Commercial material designations are supplier-specific; the product is therefore specified by glass transition temperature class, thickness class, and dielectric performance rather than by a single universal model number. Core thicknesses commonly ordered for IC package substrates include 0.10 mm, 0.14 mm, and 0.20 mm. The resin system is selected where soldering process temperatures, wire-bonding temperatures, or package warpage constraints would exceed the capability of epoxy-based FR-4 laminates. Model designations should therefore cite the core thickness, Tg class, CTE class, dielectric class, and moisture sensitivity rating rather than relying on a proprietary product code alone.
The cured network contains imide rings, triazine rings, and aromatic bridging units. Bismaleimide addition polymerization and cyanate ester cyclotrimerization proceed simultaneously during lamination, producing a crosslink density high enough to suppress segmental motion above 200 °C. Differential scanning calorimetry per IPC-TM-650 2.4.25 on a fully post-cured laminate typically reports Tg between 210 °C and 290 °C, depending on the BMI-to-cyanate ester ratio and the post-cure schedule. Dynamic mechanical analysis may report a tan-delta peak 15–30 °C higher than the DSC Tg because of the frequency dependence of the glass transition. Thermomechanical analysis per IPC-TM-650 2.4.24 shows the z-axis expansion curve departing from the glassy slope above 200 °C.
The cure exotherm of the cyanate ester fraction appears between 180 °C and 250 °C in dynamic DSC; the BMI fraction broadens the exotherm and reduces the peak heat flow compared with neat cyanate ester. The ratio of cyanate ester to bismaleimide is supplier-specific, but commercial packaging grades are formulated so that the final network retains a low dielectric constant while preventing the brittleness associated with highly triazine-rich cyanate ester homopolymers. The 5 % mass-loss temperature in nitrogen is typically above 350 °C, which provides thermal-decomposition margin during 288 °C solder float exposure.
The qualification envelope used by substrate fabricators for acceptance of BT laminate cores is summarized in Table 1. Ranges reflect differences in glass style, resin content, and supplier formulation rather than a single model.
| Property | Test method | Typical range for commercial BT laminate cores |
|---|---|---|
| Tg by DSC | IPC-TM-650 2.4.25 | 210–290 °C |
| CTE x-y, 50–150 °C | IPC-TM-650 2.4.24 | 10–14 ppm/°C |
| CTE z, 50–150 °C | IPC-TM-650 2.4.24 | 40–55 ppm/°C |
| Dk at 1 GHz | IPC-TM-650 2.5.5.13 | 3.0–3.5 |
| Df at 1 GHz | IPC-TM-650 2.5.5.13 | 0.003–0.006 |
| Water absorption, 24 h | IPC-TM-650 2.6.2.1 | 0.2–0.5 % |
| Copper peel strength | IPC-TM-650 2.4.8 | 0.8–1.2 kN/m |
The exact values for a given product are controlled by the laminate supplier’s certificate of conformance and by factory audit against the applicable IPC-4101E slash sheet. These ranges should not be used as procurement limits without supplier-confirmed data for the specific core thickness and glass style.
Lead-free assembly at 260 °C peak reflow imposes simultaneous thermal, hygroscopic, and thermomechanical stress. The glass transition above 200 °C ensures that the core remains in the glassy state during the early portion of the reflow profile, but it does not eliminate z-axis expansion. The z-axis CTE of 40–55 ppm/°C remains the primary driver for plated through-hole fatigue and via-barrel cracking after repeated reflow cycles. Moisture absorption before assembly is more critical than Tg alone. Qualification per J-STD-020 at 260 °C determines the moisture sensitivity level; BT core substrates are often classified at MSL 3 for thicknesses near 0.10 mm, but high-reliability automotive or medical packages may require MSL 2 or MSL 1, which imposes dry-pack handling, humidity indicator cards, and reduced floor life.
Solder float testing per IPC-TM-650 2.4.13 at 288 °C for 10 s is a material-level indicator and does not guarantee package-level survival at 260 °C because mold compound, die-attach, and underfill interfaces introduce additional stress. Copper adhesion after thermal stress is measured by IPC-TM-650 2.4.8; values below 0.8 kN/m after solder float are typically rejected for fine-line build-up layers. Conductive anodic filament resistance is evaluated under 85 °C and 85 % RH with an applied 100 V bias per IPC-TM-650 2.6.25. BT systems with low residual cyanate and a phosphorus-based flame retardant package generally exhibit longer time-to-failure than dicyandiamide-cured FR-4 systems.
Before lamination, BT prepreg is refrigerated at 5 °C and ≤60 % RH in moisture-barrier packaging. Ambient exposure beyond 24 h at 23 °C and 50 % RH requires reconditioning because adsorbed moisture can hydrolyze cyanate ester monomer and reduce the final crosslink density. Vacuum lamination of IC substrate cores is performed on multi-opening hot presses with platen temperatures of 190–230 °C and specific pressures of 2.5–3.5 MPa; the pressure profile is generally ramped after the resin reaches minimum melt viscosity to ensure blind-via fill without excessive resin starvation. Post-cure in a nitrogen or air-circulating oven at 220–240 °C for 1–2 h completes triazine conversion and stabilizes the DSC Tg. Batch-to-batch resin-content variation can shift gel time; press cycle programmers therefore adjust dwell time based on prepreg gel-time data. Free amine additives or amine hardeners should not be introduced into the formulation because amines catalyze cyanate ester trimerization and reduce B-stage shelf life. Strong alkaline desmear solutions above pH 12 at 80 °C can degrade the triazine network if immersion time is not controlled; plasma desmear is an alternative when fine-line adhesion retention is critical.
CO₂ laser drilling of BT cores for 50 µm blind vias typically uses pulse energies of 8–15 mJ at repetition rates of 50–60 kHz; UV laser processing is preferred for 25–40 µm vias because the shorter wavelength reduces the heat-affected zone. The aromatic triazine and imide rings raise the ablation threshold relative to epoxy FR-4, so the energy-density window shifts and may require approximately 10–20 % adjustment from epoxy baseline parameters. If the energy density is too low, the resin smears and the underlying copper is not exposed cleanly; if too high, copper melting, glass-fiber protrusion, and excessive char formation occur.
Desmear after laser drilling is validated by microsection inspection per IPC-TM-650 2.1.1 and by copper peel retention per IPC-TM-650 2.4.8. The acceptable desmear weight loss for BT is often lower than for epoxy systems; values above 0.5 mg/cm² are cause for rejection because they indicate oxidative attack on the triazine network. Production settings are equipment-specific and are normally derived by design-of-experiment runs on each laser and desmear line; published data for this specific configuration is limited.
BT resin differs from epoxy FR-4 in all critical packaging metrics. The x-y CTE is 10–14 ppm/°C compared with 16–20 ppm/°C for high-Tg FR-4, reducing die-area warpage after die attach. DSC Tg is above 200 °C compared with 135–180 °C for standard high-Tg FR-4. The dielectric constant at 1 GHz is 3.0–3.5 versus 3.8–4.5 for FR-4, which lowers propagation delay in package routing. In relation to polyimide laminates, BT absorbs less moisture—0.2–0.5 % versus 1.0–1.5 % by IPC-TM-650 2.6.2.1—and is more dimensionally stable in humid environment, though polyimide retains a higher continuous-use temperature ceiling. Compared with neat cyanate ester laminates, BT exhibits higher copper adhesion and lower brittleness because the BMI component interrupts the high-crosslink-density triazine network. Compared with ABF build-up dielectric films, BT resin is not a direct substitute; ABF is a build-up material for semi-additive fine-line redistribution, while BT resin is used as the rigid core that provides global planarity, stiffness, and CTE control. They are frequently combined in the same package substrate: a BT core with ABF build-up layers on both sides.
At 1 GHz, the dielectric constant of BT cores is 3.0–3.5 and the dissipation factor is 0.003–0.006 by IPC-TM-650 2.5.5.13. At 10 GHz, the dielectric constant may decline by 0.1–0.2 because interfacial polarization contributions decrease, while the dissipation factor may rise by 0.001–0.002 depending on moisture content and copper-foil roughness. Low-profile reverse-treated copper foil with a surface roughness around 1.5–2.0 µm Rz is often paired with BT cores to suppress conductor loss in high-speed package designs. Exact high-frequency values depend on resin content, glass style, and test method; split-post dielectric resonator or cavity techniques are used above 10 GHz because standard IPC test methods may not cover the full package-application frequency range. Published data for this specific configuration is limited, so qualification should include a coupon-level measurement on the actual core construction rather than reliance on supplier literature values alone.
Table 2 summarizes the compliance matrix commonly requested in IC packaging procurement. Values are taken from the same supplier-dependent qualification ranges and are not a universal specification.
| Requirement | Reference standard / method | Typical qualification condition |
|---|---|---|
| Flame retardance | UL 94 | V-0 at 0.10–0.20 mm core thickness |
| Halogen-free claim | IEC 61249-2-21 | Cl ≤900 ppm, Br ≤900 ppm, total halogens ≤1500 ppm |
| Glass transition | IPC-TM-650 2.4.25 | >200 °C |
| Dk / Df | IPC-TM-650 2.5.5.13 | 3.0–3.5, 0.003–0.006 at 1 GHz |
| Moisture sensitivity | J-STD-020 | MSL 3 at 260 °C peak reflow, unless higher reliability imposes MSL 2 or MSL 1 |
| Copper peel after thermal stress | IPC-TM-650 2.4.8 | 0.8–1.2 kN/m |
Operational boundaries are explicit. Continuous service in air above 250 °C is not recommended because oxidative degradation of the triazine ring becomes kinetically significant. Exposure to strong alkaline solutions above pH 12 at 80 °C requires time-limited processing with periodic microsection verification; uncontrolled exposure can reduce copper-adhesion strength. Formulators should avoid free amine additives, which accelerate cyanate ester conversion and shrink the lamination window. The selected BT core grade should also be qualified for the intended package construction, because thin-core warpage, via reliability, and die-attach compatibility are package-level properties and cannot be inferred from the resin chemistry alone.
