What governs RDL sidewall profile stability in wafer-level fan-out packaging?

In fan-out wafer-level packaging, benzocyclobutene resin is deposited as a photopatternable interlayer dielectric and stress-buffer layer over redistributed copper traces. A 300 mm production line for this application typically uses a wafer track coater with dynamic dispense, a three-zone hotplate soft-bake module, and a broadband i-line exposure tool. Film thickness after soft bake ranges from 2 µm to 25 µm depending on spin speed and resin solids content. The photosensitive formulation is adjusted to 43–50 wt% BCB resin solids dissolved in mesitylene, with a photoacid generator at 3–6 wt% of resin solids and an adhesion promoter at ≤1 wt% of resin solids. The downstream process sequence consists of vapor-phase adhesion promotion, spin coating at 800–4000 rpm, soft bake at 120–150 °C, UV exposure at 365 nm through an i-line mask aligner, puddle development at 22–23 °C, spin-rinse drying, and final cure in a nitrogen-purged oven at 250 °C for 60 min. Qualification is performed to JEDEC J-STD-020E for moisture/reflow sensitivity, JESD22-A104 for thermal cycling, and SEMI S2-0718 for equipment safety; substance restrictions are reviewed under RoHS 2011/65/EU and REACH Article 33. Terminal articles include chip-first and chip-last fan-out wafer-level package redistribution layers, automotive radar package passivation, FOCoS test vehicles, and high-density redistribution structures for high-bandwidth memory integrated substrates. Process deviation data from production-scale coaters indicate that the most recurrent defect is via sidewall scumming when hotplate temperature drifts beyond ±5 °C from recipe; controlling resin solids within ±3% between batches reduces film-thickness scatter to below ±5% on 300 mm wafers.

Millimetre-wave antenna-in-package substrate manufacturing uses BCB as a low-loss build-up dielectric between copper ground and signal structures in multilayer organic substrates. A production line for 24–77 GHz modules typically employs vacuum hot-press lamination or hot-roll lamination at 60–90 °C, followed by blind via formation with a 355 nm UV laser at a fluence of 0.5–2.0 J/cm² and plasma desmear in O₂/CF₄ at 200–400 W RF power for 30–90 s. The BCB formulation for this application is a solvent-borne thermosetting grade at 40–55 wt% resin solids; filled variants incorporate fused silica at 5–20 wt% of resin solids when coefficient of thermal expansion must be reduced from an unfilled value near 40 ppm/°C to 25–35 ppm/°C. Unfilled grades preserve low dielectric loss in the 1–10 GHz range when cured at 250 °C for 60 min under nitrogen, with extrapolation to 40 GHz verified through IPC-TM-650 2.5.5.9 testing. Qualification is additionally performed to IPC-4101 for base-material classification and JEDEC JESD22-A104 for thermal cycling; module-level moisture sensitivity is evaluated under JEDEC J-STD-020E. Terminal articles include 5G FR2 antenna-in-package modules, 77 GHz automotive radar transceiver packages, phased-array beamformer substrates, and embedded wafer-level ball grid array high-frequency redistribution layers. Production-scale process bottlenecks recorded on lamination equipment include blind-via ablation residue when plasma desmear time falls below 30 s, and lamination air entrapment when press ramp rates exceed 5 °C/min.

When optical propagation loss at 1310 nm sets the polymer waveguide budget

Because cured BCB films can produce smooth, high-resolution waveguide structures, planar lightwave circuit fabrication uses this resin as both core and cladding material. Published data for specific commercial grades places propagation loss in the range of 0.8–1.5 dB/cm at 1310 nm; performance outside this range may be attainable, though published data for this specific configuration is limited. Fabrication on silicon or glass wafers begins with spin coating a cladding layer from 45–50 wt% BCB solids in mesitylene filtered through 0.1 µm PTFE, followed by soft bake at 130–150 °C. The core layer is then spin-coated at a controlled thickness, exposed through a mask at 365 nm, and developed with solvent puddle at 22 °C. An optional upper cladding is applied before the full stack is cured in nitrogen at 250 °C for 60 min. For non-photosensitive optical grades, waveguide ribs are defined by reactive ion etching in CF₄/O₂ plasma at 10–50 mTorr and 200–400 W bias power, yielding sidewall roughness below 50 nm RMS on optimized lines. Formulation addition for optical core layers includes resin solids at 43–50 wt%, high-purity mesitylene solvent, and an antioxidant or UV absorber at ≤0.5 wt% only when environmentally exposed device operation is specified. Passive optical component qualification follows Telcordia GR-1209-CORE and GR-1221-CORE, while contamination control is maintained to ISO 14644-1 Class 5. Electronics safety and hazard documentation are aligned to SEMI S2 and REACH. Terminal articles include polymer arrayed waveguide gratings, thermo-optic mode converters, optical redistribution layers, chip-to-board optical interposers, and multichannel optical bus waveguides.

Following cavity release on a 200 mm silicon MEMS cap wafer, BCB is applied as a spin- or spray-coated bonding adhesive for wafer-level encapsulation. The adhesive formulation is a non-photosensitive solvent-bearing resin at 40–50 wt% solids, with an adhesion promoter at 0.5–2 wt% of resin solids and viscosity adjusted to 800–1200 cSt at 25 °C to limit edge starvation and chamber contamination. Production equipment includes a coater with wafer uniformity below ±5%, a proximity hotplate, a bond aligner with top and bottom heater temperature difference below ±1 °C, and a force-controlled press capable of 0.2–0.5 MPa across a 200 mm wafer. The process sequence consists of cap-wafer dehydrate bake, BCB coat at 3–8 µm thickness, soft bake at 150 °C for 10 min, alignment to the cavity wafer, thermocompression bonding at 250 °C for 60 min under nitrogen backfill, and ramp-down below 2 °C/min to reduce wafer bow. Outgassing is screened using ASTM E595; production-grade bonded wafers typically achieve total mass loss below 1% and collected volatile condensable material below 0.1%. Compliance documentation is aligned to SEMI S2, SEMI S8, ISO 14644-1 Class 5, and REACH SVHC reporting. Terminal articles include caped pressure sensors, microfluidic devices, RF-MEMS switch cavities, microbolometer vacuum references where getter integration is separate, and inertial measurement unit covers. The principal process failure mode observed is squeeze-out bridging the device trench when bond force exceeds 0.5 MPa, and void formation when residual solvent after soft bake remains above 3 wt%.

Spin-planarized passivation and field shaping in GaN HEMT fabrication

GaN-on-SiC high-electron-mobility transistor fabrication uses BCB as a spin-planarized interlayer dielectric that separates source-connected field plates from gate edges and protects the Schottky gate from ambient contamination. The resin is diluted to 30–40 wt% solids in mesitylene for this application, with an adhesion promoter added at 0.5–2 wt% of resin solids and the finished varnish filtered to 0.2 µm. Coating is performed by spin or spray coater targeting post-cure thickness from 0.5 µm to 5 µm, followed by soft bake at 120–150 °C on a proximity hotplate and cure at 250 °C for 60 min in nitrogen. Via openings through the BCB layer are formed by reactive ion etching using CF₄/O₂ chemistry at 10–50 mTorr and 200–400 W RF power, with endpoint detection by optical emission and selectivity to GaN and SiN monitored by in-situ reflectometry. Reliability qualification is performed to JEDEC JESD22-A101 for temperature-humidity-bias stress, JEP118 for reliability terminology, RoHS 2011/65/EU, and REACH; outgassing is screened to ASTM E595 where wafer-level optical integration is specified. Terminal articles include 5G base station power amplifier MMICs, X-band radar transmit/receive modules, satellite communication front-ends, and GaN power switches with die-level passivation. Process boundaries recorded on production lines include an upper cure temperature near 300 °C, beyond which dielectric darkening and loss-tangent increase occur, and a lower cure limit near 220 °C, below which solvent retention and film adhesion failure are observed.

Once copper through-silicon vias are exposed on a 2.5D passive silicon interposer, BCB is applied as a low-temperature backside passivation layer. The wafer is first backgrinded to expose copper vias, then wet-etched to produce 5–15 µm via protrusion, followed by spray coating or high-uniformity spin coating with BCB at 45–50 wt% resin solids in mesitylene. Curing is performed at 250 °C for 60 min in a nitrogen convection oven with oxygen level below 50 ppm. Via-tip openings are defined either by photosensitive BCB exposure at 365 nm or by non-photosensitive BCB dry etch in CF₄/O₂ plasma; the non-photosensitive route adds a low-temperature PECVD silicon oxide hard mask without affecting the base resin. The formulation addition for this stress-buffer application includes resin solids at 45–50 wt%, an adhesion promoter at 0.5–1 wt%, and a leveling solvent blend adjusted to achieve controlled thermal flow before crosslinking. Qualification is performed to JEDEC JESD22-A104 for thermal cycling, JESD22-A114 for electrostatic discharge robustness after passivation, SEMI S2, and REACH; electrical leakage is tested at 3.3 V or 5 V depending on interposer design. Terminal articles include passivated silicon interposers for high-bandwidth memory stacks, 2.5D GPU packages, chiplet-based application-specific integrated circuit packages, and optical interposer backside passivation. Operational boundaries include a maximum practical film thickness of 15 µm before edge cracking occurs, and a minimum via-sidewall coverage above 1 µm below which thermal-cycling reliability failures are recorded.